The traditional mobile consumer electronics such as media players and smart phones use two distinct memories, SDRAM and Flash memory. SDRAM is used as main memory since it has characteristic of byte-unit random accessibility while Flash memory as secondary storage due to its characteristic of non-volatility. However, the advent of Storage Class Memory (SCM) that supports both SDRAM and Flash memory characteristics gives an opportunity to design a new system configuration. In this paper, we explore four feasible system configurations, namely RAM-Flash, RAM-SCM, SCM-Flash and SCM-Only. Then, using a real embedded system equipped with FeRAM, a type of SCM, we analyze the tradeoffs between performance and energy efficiency of each configuration. Experimental results have shown that SCM has great potential to reduce energy consumption for all configurations while performance is highly application dependent and might be degraded on the SCM-Flash and SCM-Only configuration.

Ternary Content Addressable Memory (TCAM) is a special type of memory used in routers to achieve high-speed packet forwarding and classification. Packet forwarding is done by referring to the rules written in the routing table, whereas packet classification is performed by referring to the rules in the Access Control List (ACL). TCAM uses more transistors than Random Access Memory (RAM), resulting in high power consumption and high production cost. Therefore, it is necessary to reduce the entries written in the TCAM to reduce the transistor count. In this paper, we propose a new TCAM architecture by using Range Matching Devices (RMD) integrated within the TCAM's control logic with an optimized prefix expansion algorithm. The proposed method reduces the number of entries required to express ACL rules, especially when specifying port ranges. With less than 10 RMDs, the total number of lines required to write port ranges in the TCAM can be reduced to approximately 50%.

For the modeling of power amplifiers (PAs) using sub-Nyquist-rate sampling (sub-sampling), a quadratic down-converting architecture with a parallel-cascade method is suggested. Its performance was analyzed regarding the sampling rate below the input Nyquist rate. As a result, the model from the sub-sampling below the input Nyquist rate characterized long-term memory effects whereas the memoryless model could not. The measurement results from RF PAs with the mWiMAX signal verified the modeling performance of this architecture. Also, for the modeling of memoryless PAs, it was shown that this sub-sampled model is still effective regardless of the sampling rate.

This paper discusses an efficient discrete model for nonlinear RF power amplifier (PA) with long-term memory effects and analyzes its error. The procedure of converting RF signals and systems into a discrete domain is explained for a discrete baseband memory polynomial model. Unlike a previous simple memory polynomial model, the proposed discrete model has two different sampling frequencies: one for nonlinear system with long-term memory effects and one for input signal. A method to choose an optimal sampling frequency for the system and a discrete memory depth is proposed to minimize the sensitivity of the system for perturbation of the measured data. A two-dimensional sensitivity function which is a product of relative residual and matrix condition number is defined for least square problem of the proposed model. Examples with a wideband WiBro 3FA signal and a WCDMA 4FA signal for nonlinear transmitters are presented to describe the overall procedure and effectiveness of the proposed scheme.

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.

This paper proposes a high-speed architecture to realize two-variable numeric functions. It represents the given function as an edge-valued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD. To achieve a design, we characterize a numeric function f by the values of l and p for which f is an l-restricted Mp-monotone increasing function. Here, l is a measure of subfunctions of f and p is a measure of the rate at which f increases with an increase in the dependent variable. For the special case of an EVMDD, the EVBDD, we show an upper bound on the number of nodes needed to realize an l-restricted Mp-monotone increasing function. Experimental results show that all of the two-variable numeric functions considered in this paper can be converted into an l-restricted Mp-monotone increasing function with p=1 or 3. Thus, they can be compactly realized by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact NFGs.

Due to the detachability of Flash storage, which is a dominant portable storage, data integrity stored in Flash storages becomes an important issue. This study considers the performance of Flash Translation Layer (FTL) schemes embedded in Flash storages in conjunction with file system behavior that pursue high data integrity. To assure extreme data integrity, file systems synchronously write all file data to storage accompanying hot write references. In this study, we concentrate on the effect of hot write references on Flash storage, and we consider the effect of absorbing the hot write references via nonvolatile write cache on the performance of the FTL schemes in Flash storage. In so doing, we quantify the performance of typical FTL schemes for a realistic digital camera workload that contains hot write references through experiments on a real system environment. Results show that for the workload with hot write references FTL performance does not conform with previously reported studies. We also conclude that the impact of the underlying FTL schemes on the performance of Flash storage is dramatically reduced by absorbing the hot write references via nonvolatile write cache.

Orthogonal frequency division multiplexing (OFDM) signals have high peak-to-average power ratio (PAPR) and cause large nonlinear distortions in power amplifiers (PAs). Memory effects in PAs also become no longer ignorable for the wide bandwidth of OFDM signals. Digital baseband predistorter is a highly efficient technique to compensate the nonlinear distortions. But it usually has many parameters and takes long time to converge. This paper presents a novel predistorter design using a set of orthogonal polynomials to increase the convergence speed and the compensation quality. Because OFDM signals are approximately complex Gaussian distributed, the complex Hermite polynomials which have a closed-form expression can be used as a set of orthogonal polynomials for OFDM signals. A differential envelope model is adopted in the predistorter design to compensate nonlinear PAs with memory effects. This model is superior to other predistorter models in parameter number to calculate. We inspect the proposed predistorter performance by using an OFDM signal referred to the IEEE 802.11a WLAN standard. Simulation results show that the proposed predistorter is efficient in compensating memory PAs. It is also demonstrated that the proposal acquires a faster convergence speed and a better compensation effect than conventional predistorters.

This paper describes a time-domain expression based on the physical model of power amplifiers where electric memory effect is considered to be caused by even-order nonlinearity and bias impedance. It is demonstrated that the time-domain expression is consistent with the general memory polynomial reported by D.R. Morgan et al. To confirm validity of the physical model, a simple method is proposed to measure amplitude and phase of IMD by two tone test: the phase is extracted from measured small signal S-parameters of the amplifier under test. The method is applied to a GaN FET amplifier under condition that memory effect is enhanced by applying inductive cable for DC supply. Frequency dependent IMD is fitted by a parallel connection of L, C, and R: it has been confirmed that the frequency dependence of IMD is given by the bias impedance at even order harmonics of envelope frequency. The frequency dependence assures the validity of the physical model as well as the time-domain expression.

This paper presents a digital predistorter with a wideband memory effect compensator for a Doherty power amplifier (PA). A simple memory-predistortion model, which consists of a look-up-table (LUT) and an adaptive filter equalizing memory effects, and a new memory effect estimation algorithm using a direct-learning architecture are proposed. The proposed estimation algorithm has an advantage that a transfer function of a feedback circuit does not affect the learning process. The predistorter is implemented in a field programmable gate array (FPGA) and a digital signal processor (DSP). The transmitter has achieved distortion level of -50.8 dBr at signal bandwidth away from the carrier, and PA module efficiency of 24% with output power of 43 dBm at 2595 MHz under a 20 MHz-bandwidth orthogonal frequency division multiplexing (OFDM) signal using laterally diffused metal oxide semiconductor (LDMOS) FETs.

An inter-modulation distortion (IMD) compensation method for thermal memory effect using a multistage RC-ladder circuit has been proposed. The IMD caused by the thermal memory effect on an InGaP/GaAs HBT amplifier was compensated for by inserting a multistage RC-ladder circuit in the base bias circuit of the amplifier. Since heat flux owing to self-heating in the transistor can be approximated with a multistage thermal RC-ladder circuit, the canceling of IMD by an additional electrical memory effect generated from the RC-ladder circuit is predicted. The memory effects cause asymmetrical characteristics between upper and lower IMD. The IMD caused by the memory effects is expressed as a vector sum of each origin. By adjusting an electrical reactance characteristic for sub-harmonics affected by the thermal memory effect in the amplifier circuit, the asymmetric characteristic is symmetrized. The parameters of the RC-ladder circuit were estimated so that the adjusted electrical reactance characteristic is reproduced in simulation. A fabricated InGaP/GaAs HBT amplifier with the thermal memory effect compensation circuit exhibited a symmetrized and suppressed IMD characteristics.

This letter introduces a buffer management issue in designing SSDs for log-structured file systems (LFSs). We implemented a novel trace-driven SSD simulator in SystemC language, and simulated several SSD architectures with the NILFS2 trace. From the results, we give two major considerations related to the buffer management as follows. (1) The write buffer is used as a buffer not a cache, since all write requests are sequential in NILFS2. (2) For better performance, the main architectural factor is the bus bandwidth, but 332 MHz is enough. Instead, the read buffer makes a key role in performance improvement while caching data. To enhance SSDs, accordingly, it is an effective way to make efficient read buffer management policies, and one of the examples is tracking the valid data zone in NILFS2, which can increase the data hit ratio in read buffers significantly.

File systems make use of the buffer cache to enhance their performance. Traditionally, part of DRAM, which is volatile memory, is used as the buffer cache. In this paper, we consider the use of of Non-Volatile RAM (NVRAM) as a write cache for metadata of the file system in embedded systems. NVRAM is a state-of-the-art memory that provides characteristics of both non-volatility and random byte addressability. By employing NVRAM as a write cache for dirty metadata, we retain the same integrity of a file system that always synchronously writes its metadata to storage, while at the same time improving file system performance to the level of a file system that always writes asynchronously. To show quantitative results, we developed an embedded board with NVRAM and modify the VFAT file system provided in Linux 2.6.11 to accommodate the NVRAM write cache. We performed a wide range of experiments on this platform for various synthetic and realistic workloads. The results show that substantial reductions in execution time are possible from an application viewpoint. Another consequence of the write cache is its benefits at the FTL layer, leading to improved wear leveling of Flash memory and increased energy savings, which are important measures in embedded systems. From the real numbers obtained through our experiments, we show that wear leveling is improved considerably and also quantify the improvements in terms of energy.

The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

A HfO2 as the charge-storage layer with the physical thickness thinner than 4 nm in silicon-oxide-high-k oxide-oxide-silicon (SOHOS) flash memory was investigated. Compared to the conventional silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, the SOHOS shows the slow operational speed and exhibits the poorer retention characteristics. These are attributed to the thin physical thickness below 4 nm and the crystallization of the HfO2 to contribute the lateral migration of the trapped charge in the trapping layer during high temperature annealing process.

In this paper, it is shown that our fabricated MTJ of 60180 nm2, which is connected to the MOSFET in series by 3 levels via and 3 levels metal line, can dynamically operate with the programming current driven by 0.14 µm CMOSFET. In our measurement of transient characteristic of fabricated MTJ, the pulse current, which is generated by the MOSFET with an applied pulse voltage of 1.5 V to its gate, injected to the fabricated MTJ connected to the MOSFET in series. By using the current measurement technique flowing in MTJ with sampling period of 10 nsec, for the first time, we succeeded in monitor that the transition speed of the resistance change of 60180 nm2 MTJ is less than 30 ns with its programming current of 500 µA and the resistance change of 1.2 kΩ.

In this work, we propose a scheme of routing table compaction for IP forwarding engines based on ternary content addressable memory (TCAM). Our scheme transforms the original routing table into a form with only disjoint prefixes. The most prevalent next hop of the routing table is then calculated and the route prefixes corresponding to the next hop are replaced by one TCAM entry. In combination with Espresso-II logic minimization algorithm, the proposed scheme reduces the TCAM storage requirements by more than 75% compared to the original routing tables. We also present an effective approach to support incremental updates.

In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.

Nonlinear distortions in power amplifiers (PAs) generate spectral regrowth at the output, which causes interference to adjacent channels and errors in digitally modulated signals. This paper presents a novel method to evaluate adjacent channel leakage power ratio (ACPR) and error vector magnitude (EVM) from the amplitude-to-amplitude (AM/AM) and amplitude-to-phase (AM/PM) characteristics. The transmitted signal is considered to be complex Gaussian distributed in orthogonal frequency-division multiplexing (OFDM) systems. We use the Mehler formula to derive closed-form expressions of the PAs output power spectral density (PSD), ACPR and EVM for memoryless PA and memory PA respectively. We inspect the derived relationships using an OFDM signal in the IEEE 802.11a WLAN standard. Simulation results show that the proposed method is appropriate to predict the ACPR and EVM values of the nonlinear PA output in OFDM systems, when the AM/AM and AM/PM characteristics are known.

Robot path-planning is one of the important issues in robotic navigation. This paper presents a novel robot path-planning approach based on the associative memory using Self-Organizing Incremental Neural Networks (SOINN). By the proposed method, an environment is first autonomously divided into a set of path-fragments by junctions. Each fragment is represented by a sequence of preliminarily generated common patterns (CPs). In an online manner, a robot regards the current path as the associative path-fragments, each connected by junctions. The reasoning technique is additionally proposed for decision making at each junction to speed up the exploration time. Distinct from other methods, our method does not ignore the important information about the regions between junctions (path-fragments). The resultant number of path-fragments is also less than other method. Evaluation is done via Webots physical 3D-simulated and real robot experiments, where only distance sensors are available. Results show that our method can represent the environment effectively; it enables the robot to solve the goal-oriented navigation problem in only one episode, which is actually less than that necessary for most of the Reinforcement Learning (RL) based methods. The running time is proved finite and scales well with the environment. The resultant number of path-fragments matches well to the environment.