This paper proposes the synchronization control method for two different unified chaotic systems with unknown mismatched parameters using sum of squares method. Previously, feedback-linearizing and stabilization terms were used in the controller for the synchronization problem. However, they used just a constant matrix as a stabilization control gain, whose performance is shown to be valid only for a linear model. Thus, we propose the novel control method for the synchronization of the two different unified chaotic systems with unknown mismatched parameters via sum of squares method. We design the stabilization control input which is of the polynomial form by sum of squares method and also the adaptive law for the estimation of the unknown mismatched parameter between the master and slave systems. Since we can use the polynomial control input which is dependent on the system states as the stabilization controller, the proposed method can have better performance than the previous methods. Numerical simulations for both uni-directional and bi-directional chaotic systems show the validity and advantage of the proposed method.

In this paper, we introduce an approach of service adaptation for behavior mismatching services using pushdown model checking. This approach uses pushdown systems as model of adaptors so that capturing non-regular behavior in service interactions is possible. Also, the use of pushdown model checking integrates adaptation and verification. This guarantees that an adaptor generated by our approach not only solves behavior mismatches but also satisfies usual verification properties if specified. Unlike conventional approaches, we do not count on specifications of adaptor contracts but take only information from behavior interfaces of services and perform fully automated adaptor generation. Three requirements relating to behavior mismatches, unbounded messages, and branchings are retrieved from behavior interfaces and used to build LTL properties for pushdown model checking. Properties for unbounded messages, i.e., messages sent and received arbitrary multiple times, are especially addressed since it characterizes non-regular behavior in service composition. This paper also shows some experimental results from a prototype tool and provides directions for building BPEL adaptors from behavior interface of generated adaptor. The results show that our approach does solve behavior mismatches and successfully capture non-regular behavior in service composition under the scale of real service applications.

This paper considers a simple type of Dynamic Element Matching (DEM), Clocked Averaging (CLA) method referred to as one-element-shifting (OES) and its effectiveness for the implementation of high spurious-free dynamic range (SFDR) multi-bit Delta-Sigma modulators (DSMs). Generic DEM techniques are successful at suppressing the mismatch error and increasing the SFDR of data converters. However, they will induce additional glitch energy in most cases. Some recent DEM methods achieve improvements in minimizing glitch energy but sacrificing their effects in harmonic suppression due to mismatches. OES technique discussed in this paper can suppress the effect of glitch while preserving the reduction of element mismatch effects. Hence, this approach achieves better SFDR performance over the other published DEM methods. With this OES, a 3rd order, 10 MHz bandwidth continuous-time DSM is implemented in 90 nm CMOS process. The measured SFDR attains 83 dB for a 10 MHz bandwidth. The measurement result also shows that OES improves the SFDR by higher than 10 dB.

Current sources are essential components for analog circuit designs, the mismatch of which causes the significant degradation of the circuit performance. This paper addresses the mismatch model of CMOS current sources, unlike the conventional modeling, focusing on the layout- and λ-dependency of the process variation, where λ is the output conductance parameter. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90 nm process technology, where we can collect the characteristics variation data for MOSFETs of various layouts. The test chip also includes D/A converters to check the differential non-linearity (DNL) caused by the mismatch of current sources when behaving as a DAC. Identifying the variation and the circuit-level errors in the measured DNLs, we reveal that our model can more accurately account for the current variation compared to the conventional mismatch model.

This paper suggests an outphasing scheme to reduce adjacent channel spectral regrowth triggered by the gain and phase mismatch between two signal paths in linear amplification with nonlinear component (LINC) systems. The error vector magnitude and power spectral density of the output signal considering path mismatch are described analytically using path mismatch factor. An outphasing scheme is proposed to reduce the spectral regrowth. The proposed outphasing scheme reshapes the phases of the separated signals in LINC systems to reduce the changes of the phases. Its performance is verified by performing simulations with multi-tone signals. The result shows that the scheme can reduce the spectral regrowth of the multi-tone signals significantly compared to the conventional outphasing scheme for LINC systems with path imbalance.

For analog applications, the Metal-Insulator-Metal (MIM) capacitance has to be measured at a much higher resolution than using the conventional methods, i.e. to a sub-femto level. A new robust mismatch measurement technique is proposed, which is more accurate and robust compared to the conventional Floating Gate Capacitance Measurement (FGCM) methods. A capacitance mismatching measurement methodology based on Vs is more stable than that based on Vf because the influence of pre-existing charge in the floating-gate can be cancelled in the slope of ΔVs/ΔVf based on Vs. The accuracy of this method is evaluated through silicon measurement in a 0.13 µm technology. It shows that, compared to the ideal value, the average of the new method are within 0.12% compared to 49.23% in conventional method while the standard deviation is within 0.15%.

Device mismatch plays an important role in the design of accurate analog circuits. The common centroid structure is commonly employed to reduce device mismatches caused by symmetrical layouts and processing gradients. Among the candidate placements generated by the common centroid approach, however, whichever achieves better matching is generally difficult to be determined without performing the time-consuming yield evaluation process. In addition, this rule-based methodology makes it difficult to achieve acceptable matching between multiple capacitors and to handle an irregular layout area. Based on a spatial correlation model, this study proposed a design methodology for yield enhancement of analog circuits using switched-capacitor techniques. An efficient and effective placement generator is developed to derive a placement for a circuit to achieve the highest or near highest correlation coefficient and thus accomplishing a better yield performance. A simple yield analysis is also developed to evaluate the achieved yield performance of a derived placement. Results show that the proposed methodology derives a placement which achieves better yield performance than those generated by the common centroid approach.

This paper presents a calibration scheme for delay mismatch between envelope and phase in the OFDM polar transmitter. An asynchronous delay detection method is proposed to avoid using a complicated signal processing algorithm or synchronous elements which need high clocking rates for detecting small delay mismatch. This scheme uses buffer delay chains to estimate the mismatch and then the estimated delay values are asynchronously stored in registers. It is verified that the proposed scheme well suites application to the OFDM polar transmitter through SPW, Matlab and HDL simulations. It achieves the margin of about 20 dB at 20 MHz offset, 10 dB at 40 MHz offset in terms of spectral limit specified in WLAN standard.

This paper focuses on the problem of performance degradation in mismatched speech recognition. The F-Ratio analysis method is utilized to analyze the significance of different frequency bands for speech unit classification, and we find that frequencies around 1 kHz and 3 kHz, which are the upper bounds of the first and the second formants for most of the vowels, should be emphasized in comparison to the Mel-frequency cepstral coefficients (MFCC). The analysis result is further observed to be stable in several typical mismatched situations. Similar to the Mel-Frequency scale, another frequency scale called the F-Ratio-scale is thus proposed to optimize the filter bank design for the MFCC features, and make each subband contains equal significance for speech unit classification. Under comparable conditions, with the modified features we get a relative 43.20% decrease compared with the MFCC in sentence error rate for the emotion affected speech recognition, 35.54%, 23.03% for the noisy speech recognition at 15 dB and 0 dB SNR (signal to noise ratio) respectively, and 64.50% for the three years' 863 test data. The application of the F-Ratio analysis on the clean training set of the Aurora2 database demonstrates its robustness over languages, texts and sampling rates.

In this letter, we propose a novel approach to estimate three different kinds of phone mismatch penalty matrices for two-stage keyword spotting. When the output of a phone recognizer is given, detection of a specific keyword is carried out through text matching with the phone sequences provided by the specified keyword using the proposed phone mismatch penalty matrices. The penalty matrices associated with substitution, insertion and deletion errors are estimated from the training data through deliberate error generation. The proposed approach has shown a significant improvement in a Korean continuous speech recognition task.

Reflecting the rapid growth of information technology, the configuration of software applications such as word processors and spreadsheets is both sophisticated and complicated. It is often difficult for users to identify relevant functions in the online manual for a target application. In this paper, we propose a method for question answering that finds functions related to the user's request. To enhance our method, we addressed two "mismatch" problems. The first problem is associated with a mismatch in vocabulary, where the same concept is represented by different words in the manual and in the user's question. The second problem is associated with a mismatch in function. Although the user may have a hypothetical function for a purpose in mind, this purpose can sometimes be accomplished by other functions. To resolve these mismatch problems, we extract terms related to software functions from the Web, so that the user's question can be matched to the relevant function with high accuracy. We demonstrate the effectiveness of our method experimentally.

It is well known that the performance of CDMA systems may degrade in the presence of spreading code mismatch. The diagonal loading multiple constrained minimum variance (DL-MCMV) approaches have been proposed to deal with the mismatch problem. However, they still cannot improve the robust capability efficiently due to the spreading code mismatch. In this letter, a detector based on the variable DL technique is presented that offers more robust capabilities than the MCMV and DL-MCMV detectors. Computer simulation results are provided that illustrate the effectiveness of the proposed detector.

In direct-conversion orthogonal frequency division multiplexing (OFDM) receivers, the impact of frequency-dependent I/Q mismatch (IQ-M) with carrier frequency offset (CFO) must be considered. A preamble-assisted estimation is developed to circumvent the frequency-dependent IQ-M with CFO. The results of a simulation and an experiment show that the proposed method could provide good estimation efficiency and enhance the system performance. Moreover, the proposed scheme is compatible with current wireless local area network standards.

Time-interleaving is an efficient approach to increase the effective sampling rate of the ΣΔ modulators, but time-interleaved (TI) ΣΔ modulators are sensitive to channel mismatch, which causes the quantization noise folded back into the band of interest. To reduce the folded noise caused by the channel mismatch of two-channel TI ΣΔ modulators, a low-power second-order two-channel TI ΣΔ modulator is proposed. The noise transfer function (NTF) of the modulator is a band-pass filter. By using this band-pass NTF, the folded noised can be reduced. The entire modulator can be implemented by employing three op-amps, which is beneficial for power consumption. The circuit of implementation for the proposed modulator is designed in 0.18 µm COMS technology. The proposed modulator can achieve a SNDR of 78.9 dB with a channel mismatch of 0.5% and a linear gradient mismatch of 0.4% for unity sampling capacitors. Monte Carlo simulation is done with a random Gaussian mismatch of 0.4% standard deviation for all capacitors, resulting in an average SNDR of 80.5 dB. It is indicated that the proposed TI modulator is insensitive to the channel mismatch. The total power consumption is 19.5 mW from a 1.8 V supply.

Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.

A new analog mismatch model in circuit level has been developed. MOS transistor's small signal parameters are modeled in term of their matching character for both strong- and weak-inversion operations. Mismatch analysis on basic CMOS amplifiers are conducted with proposed model and Monte Carlo SPICE simulations. We successfully derived simple analytical formula on performance mismatch for analog CMOS circuits, which is verified to be accurate in using actual analog circuit design, within an average error of less than 10%.

This letter proposes a mismatch insensitive switched-capacitor multiply-by-four (4X) amplifier using the voltage addition scheme. The proposed circuit provides 2-times faster speed and about half of silicon area when compared with the cascade of conventional 2X amplifiers. Monte-Carlo simulation results show about 15% gain accuracy improvement over the cascaded 2X- amplifiers.

The performance of an analog winner-take-all (WTA) circuit is affected by the corner error and the offset error. Despite the fact that the corner error can be reduced with large transconductance of the transistor, the offset error caused by device mismatch has not been completely studied. This paper presents the complete offset error analysis, and proposes low offset design guidelines and an offset cancellation scheme. The experimental results show good agreement with the theoretical analysis and the drastic improvement of the offset error.

This paper proposes a new charge pump to suppress spurious noise of phase-locked loops. The spurious noise is induced by charge injection generated from the parasitic capacitors associated with switches and the current-mismatch between the charging and discharging currents of the charge pump. A new charge pump is configured by adding an operational amplifier, a sample-and-hold circuit, and switches to a basic charge pump. During the idling time of the charge pump, the currents of the current sources are adjusted and the current-mismatch are reduced to 0.3%. Applying the proposed charge pump to a phase-locked loop, we can suppress the spurious noise by 18 dB compared with a PLL using a basic one.

In this letter, a decision-directed MOE detector with excellent robustness against signature waveform mismatch is proposed for DS-CDMA systems. Both the theoretic analysis and computer simulation results demonstrate that the proposed detector can provide better SINR performance than that of conventional detectors.