A reduced complexity multiple-input multiple-output (MIMO) equalizer with ordered successive interference cancellation (OSIC) is proposed for combating intersymbol interference (ISI) and cochannel interference (CCI) over frequency-selective multipath channels. It is developed as a reduced-rank realization of the conventional MMSE decision feedback equalizer (DFE). In particular, the MMSE weight vectors at each stage of OSIC are computed based on the generalized sidelobe canceller (GSC) technique and reduced-rank processing is incorporated by using the conjugate gradient (CG) algorithm for reduced complexity implementation. The CG algorithm leads to a best low-rank representation of the GSC blocking matrix via an iterative procedure, which in turn gives a reduced-rank equalizer weight vector achieving the best compromise between ISI and CCI suppression. With the dominating interference successfully cancelled at each stage of OSIC, the number of iterations required for the convergence of the CG algorithm decreases accordingly for the desired signal. Computer simulations demonstrate that the proposed reduced-rank MIMO DFE can achieve nearly the same performance as the full-rank MIMO MMSE DFE with an effective rank much lower than the dimension of the signal-plus-interference subspace.

With the progress of integration of circuits and PCBs (Printed Circuit Boards), novel techniques have been required for verification of signal integrity. Noise analysis of the power/ground planes is one of the most important issues. This paper describes a high-speed simulator for PCBs which contain the interconnects with nonlinear terminations. This simulator is based on the environmental tool ASSIST (Assistant System for Simulation Study) constructed for development of the circuit simulators, and is combined with PRIMA (Passive Reduced-Order Interconnect Macromodeling Algorithm). In this simulator, an efficient implementation of PRIMA is considered with using a voltage-controlled current source (VCCS) model. Finally, this simulator is applied to the analysis of power/ground planes of the simple PCBs, and the validity is verified.

This paper considers a high-rate turbo code which employs high-rate convolutional codes as component codes, and presents a novel method of reducing the decoding complexity of the codes. By eliminating some of branches that have the lowest reliabilities among all the branches entering each node, the proposed algorithm reduces the complexity in the process of the add-compare-select (ACS) between the consecutive stages of iterative decoding. That is, the complexity gradually decreases as the number of iterations increases. We compare the unpunctured high-rate turbo code with a classical punctured high-rate turbo code in terms of performance/complexity trade-off under the same code rate. Simulation results show that the proposed approach with a good trade-off provides an alternative coding scheme to the classical punctured high-rate turbo coding for the application to high-data-rate wireless communication systems.

The encryption and the decryption of the product-sum type public key cryptosystems can be performed extremely fast. However, when the density is low, the cryptosystem should be broken by the low-density attack. In this paper, we propose a new class of the product-sum type public key cryptosystems based on the reduced bases, which is invulnerable to the low-density attack.

We investigate traffic performance of CBWL schemes with multimedia services on non-homogeneous cellular network in which cut-off priority is given to handoff calls. Two generic routing schemes are analyzed: one is the randomized routing and the other is the least loaded routing. The performance measures that we focus on are the new call blocking probabilities and the handoff failure probabilities. To evaluate blocking probabilities of interest, we construct a generalized access network whose blocking probabilities are same as ones for CBWL systems. For analysis of generalized access network, we apply the reduced load approximation. The computational complexity and memory requirements of proposed algorithm are linear so that we can use this algorithm to approximate blocking probabilities of CBWL systems of large size. The proposed approximations are tested on a number of simple examples. Numerical results for 12 cells and 36 cells networks are given. The comparison between approximation and simulation results shows that the proposed approximation method is quite accurate.

This paper summarizes power reduction methods applicable for VLSI bus systems in terms of reduction of signal swing, effective capacitance reduction and reduction of signal transition, which have been studied in authors' research group. In each method the basic concept is reviewed quickly along with some examples of its application. A future perspective is also described in conclusion.

Two-dimensional (2-D) adaptive digital filters (ADFs) for 2-D signal processing have become a fascinating area of the adaptive signal processing. However, conventional 2-D FIR ADF's require a lot of computations. For example, the TDLMS requires 2N2 multiplications per pixel. We propose a new 2-D adaptive filter using the FFTs. The proposed adaptive filter carries out the fast convolution using overlap-save method, and has parallel structure. Thus, we can reduce the computational complexity to O(log2N) per pixel.

In this paper, we propose a new multicast routing algorithm for constructing the delay-constrained minimal spanning tree in the VP-based ATM networks, in which we consider the efficiency even in the case where the destination dynamically joins/departs the multicast connection. For constructing the delay-constrained spanning tree, we first generate a reduced network consisting of only VCX nodes from a given ATM network, originally consisting of VPX/VCX nodes. Then, we obtain the delay-constrained spanning tree with a minimal tree cost on the reduced network by using our proposed heuristic algorithm. Through numerical examples, we show that our dynamic multicast routing algorithm can provide an efficient usage of network resources when the membership nodes frequently changes during the lifetime of a multicast connection, while the existing multicast routing algorithm may be useful for constructing the multicast tree with a static nature of destination nodes. We also demonstrate that more cost-saving can be expected in dense networks when applying our proposed algorithm.

The recent progress of B-ISDN signaling systems has enabled networks to handle calls which require a wide variety of ATM connection sets. This paper is concerned with the circuit group which handles calls requesting asymmetric forward and backward multi-connections, and has the capability of both bandwidth negotiation and bandwidth reservation as a traffic control for enhancing call blocking performance. A model of the circuit group is first established focusing on the call level characteristics of the group, and then a method based on the reduced load approximation and an approximate analysis of a multirate group is proposed for calculating approximate blocking probabilities. The accuracy of the approximation method is evaluated numerically by comparing with an exact method and simulation. Further the impact of bandwidth negotiation and reservation on call blockings is examined based on numerical examples.

This paper describes an advanced rule-embedded neural network (RENN+) that has an extended framework for achieving a very tight integration of learning-based neural networks and rule-bases of existing if-then rules. The RENN+ is effective in pattern recognition with ill-posed conditions. It is basically composed of several component RENNs and an output RENN, which are three-layer back-propagation (BP) networks except for the input layer. Each RENN can be pre-organized by embedding the if-then rules through translation of the rules into logic functions in a disjunctive normal form, and can be trainded to acquire adaptive rules as required. A weight-modification-reduced learning algorithm (WMR) capable of standard regularization is used for the post-training to suppress excessive modification of the weights for the embedded rules. To estimate the effectiveness of the proposed RENN+, it was used for pattern recognition in a radar system for detection of buried pipes. This trial showed that a RENN+ with two component RENNs had good recognition capability, whereas a conventional BP network was ineffective.

This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.

A new Viterbi algorithm with adaptive path reduction method is presented. The proposed system consists of the pre-decoder and reduced path Virerbi decoder. The predecoder separates the mixed channel noise from the received sequence. The number of errors in the pre-decoded error sequence is counted and the path reduction is implemented by the number of errors in pre-decoded error sequence. The path reduction is implemented as a function of channel condition because the errors in the pre-decoded error sequence can be considered as the channel error sequence. Due to the reduction of the path, the number of ACS (add compare select) operations can be reduced, which occupies the dominant part in Viterbi decoding. The ACS reduction ratio for the proposed system achieves up to 30% for the case of (2, 1, 2) Ungerboeck code without degradation of the error performance.

The performance evaluation by analysis of systems employing Reduced State Viterbi decoding is addressed. This type of decoding is characterized by an inherent error propagation effect, which yields a difficulty in the error probability analysis, and has been usually neglected in the literature. By modifying the Full State trellis diagram, we derive for Reduced State schemes, new transfer function bounds with the effects of error propagation. Both the Chernoff and the tight upper bound are applied to the transfer function in order to obtain the bit error probability upper bound. Furthermore, and in order to get a tighter bound for Reduced State decoding schemes with parallel transitions, the pairwise probability of the two sequences involved in an error event is upper bounded, and then the branch metric of a sequence taken from that bound is associated with a truncated instead of complete Gaussian noise probability density function. To support the analysis, particular assessment is done for a Trellis Coded Modulation scheme.

A new optical interconnection system suitable for high-speed ICs using a novel complementary optical interconnection technique has been developed. This system uses paired light sources and photodetectors for optical complementary operation, and greatly lowers the power consumption compared with conventional systems. Analyses and experimental results indicate that this system can operate in the gigabit range, and reduces power consumption to less than 20% of that in conventional systems at 1 Gb/s.

This paper surveys modeling techniques for telephone call control based on a Finite State Machine (FSM) concept, and studies model simplification techniques. First, the basic concept and fundamental issues of call control modeling are described. Then, based on the analysis of layered call control configuration, it is clarified that the call control machine decomposition within the two-party service control layer has the effect of reducing the apparent size of each mate's machine. Using this effect, guidelines for call control modeling are derived, by which multiple services can be modeled independently. Finally implementation techniques and a few examples of application will be presented.