Software defined radio (SDR) is receiving much attention as the key technology to realize the next generation wireless communication system. This paper proposes the concept of system diversity on SDR and investigates the effectiveness of system diversity by using a concrete simulation model. System diversity allows the wireless communication system being used to be dynamically changed in addition to the signal processing algorithm or modulation/coding scheme being used. To clarify the validity of system diversity, we examine a system simulation model consisting of three wireless communication systems; algorithms are introduced to show how system diversity can be controlled using the QoS parameters of received signal level, data transmission rate, and channel capacity. The process by which system diversity switching is triggered is elucidated, and a practical example is introduced. Simulation results confirm that system diversity offers higher performance in terms of data throughput and system channel capacity than existing wireless communication systems. Finally, a comprehensive algorithm is described that protects existing single-mode traffic from being degraded by SDR switching.

CRL (Communications Research Laboratory, Independent Administrative Institution Japan) is developing a road to vehicle multiple-service communication system based on RoF (Radio over Fiber) technology in a millimeter-wave frequency region of 36-37 GHz. In the experimental system, vehicle can receive three wireless services such as PHS (Personal Handy-phone System), ETC (Electronic Toll Collection system), SB (Satellite Broadcasting). In this paper, the system concept and experimental system configuration are introduced. Furthermore, SDR (Software Defined Radio) mobile terminal technology is mentioned and a new concept for a next generation mobile communication network system based on RoF is proposed.

A knowledge gap between network operators and system developers in Network Management System (NMS) construction has widened. This has been caused by an expansion of supported business processes and increasingly sophisticated network management functions. This gap makes system development costly and time consuming. Function development, led by operators, is a promising solution to the problems caused by the gap. This type of development should not require an operator to know how to develop NMS. Standard objects may be used to meet this requirement and save time and the cost of NMS construction. However, they are not sufficient to design functions supporting some tasks that are for providing custom services. In this paper, we propose a partial extension package, composed of several object classes. This package is attached to the standard objects to design a custom function. Information processing in a new function can be added, and easily modified, using this package. This package specifies states that invoke the information processing. It also includes objects that add new data without changing standard objects. It makes use of several design patterns in order to weaken coupling to the standard objects. We have applied this package to two programs. One plans maintenance tasks schedules, the other sets threshold values for quality of service. We made use of software metrics to measure their performance in terms of flexibility. The results show that the proposed package continues to make it possible to reuse the standard objects, and makes it easy to modify the behavior of a new function.

A symbol timing synchronization method is proposed for the realization of a multi-mode and multi-service software radio receiver. The method enables an accurate search for the optimum symbol timing without any redundant hardware such as sampling rate conversion devices, when the system clock is non-integer times for the target systems' symbol rates. Accordingly, a multimode and multi-service receiver can set an arbitrary system clock for the target systems' symbol rates, and the number of A/D converters can be reduced to the minimum. Also, it may lead to a reduction of the implementation time for digital signal processing hardware, and reduce the burden on the memory in a multi-mode and multi-service software radio receiver, since no sampling rate conversion is needed. The effectiveness of the proposed method for use with a multi-mode and multi-service software radio receiver for future ITS services, which are GPS (Global Positioning System), ETC (Electric Toll Collection system), and Japanese PHS (Personal Handy-phone System) is assumed, and the supposed system is evaluated by computer simulation. The jitter performance under an AWGN (Additive White Gaussian Noise) environment is first simulated, and the necessary number of over-samples and observation symbols are defined by the value of jitter which gives a theoretical value of the BER, respectively. Moreover, the bit error rate performance under a fading environment condition where the attenuation of a signal level fluctuates more rapidly than in a noise environment is calculated, and it is shown that the proposed method enables an accurate search for the optimum synchronization timing caused by a cycle slip even if the signal level is quite low, and allows one handset to adopt a system clock for several systems.

Adaptation of software components to the requirements is one of the key concerns in Component Based Software Development (CBSD). In this paper, we propose a formal approach to compose component based systems which are adaptable to the requirements. We focus on the functional aspects of software components and requirements, which are expressed in S-sorted functions. Those S-sorted functions are transformed into Colored Petri Nets (CPN) models in order to evaluate connectivity between the components, and to evaluate adaptability of composed systems to the requirements. The connectivity is measured based on colors or data types in CPN, while the adaptability is measured based on functional equivalency. We introduce simple glue codes to connect the components each other. The paper focuses on business applications, however the proposed approach can be applied to any other domains as far as the functional adaptability is concerned.

A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.

The hardware-software codesign of distributed embedded systems is a more challenging task, because each phase of codesign, such as copartitioning, cosynthesis, cosimulation, and coverification must consider the physical restrictions imposed by the distributed characteristics of such systems. Distributed systems often contain several similar parts for which design reuse techniques can be applied. Object-oriented (OO) codesign approach, which allows physical restriction and object design reuse, is adopted in our newly proposed Distributed Embedded System Codesign (DESC) methodology. DESC methodology uses three types of models: Object Modeling Technique (OMT) models for system description and input, Linear Hybrid Automata (LHA) models for internal modeling and verification, and SES/workbench simulation models for performance evaluation. A two-level partitioning algorithm is proposed specifically for distributed systems. Software is synthesized by task scheduling and hardware is synthesized by system-level and object-oriented techniques. Design alternatives for synthesized hardware-software systems are then checked for design feasibility through rapid prototyping using hardware-software emulators. Through a case study on a Vehicle Parking Management System (VPMS), we depict each design phase of the DESC methodology to show benefits of OO codesign and the necessity of a two-level partitioning algorithm.

In software-based wireless multimedia communications systems, each mobile terminal will be able to select its best-suited transmission format according to its quality of service (QoS) and channel condition. In this paper, we focus attention on "access scheme selectability" in such a software-based system, and discuss the traffic performance improvement due to adaptive access scheme selection. Assuming a software-based TDMA/CDMA system where time division multiple access (TDMA) and direct sequence code division multiple access (DS-CDMA) schemes are flexibly selectable, we evaluate the traffic performance in terms of average delay with a typical multimedia service model to be supported in future wireless communications systems. In the TDMA/CDMA system, how to determine an appropriate access scheme for a user is a key issue. Therefore, we discuss the selection algorithm for efficiently supporting heterogeneous multimedia services. Our computer simulation results show that the software-based system with a simple access scheme selection algorithm can significantly improve the traffic performance as compared with conventional hardware-based systems.

Message Sequence Chart (MSC) standardized by International Telecommunication Union is a graphical and textual language for specification of concurrent systems. It has been used formally as well as informally to specify behavior of real-time systems, in particular telecommunication switching systems. Formal verification of a system specification is crucial to ensure that implementation of the system works correctly. In particular, verification methods based on finite states have been widely used in telecommunication systems design. The methods determine global system states and transitions between them (i. e. , build a global state transition graph (GSTG)), and verify the system's desired properties, such as safety and liveness, on the GSTG. In this paper, we focus on construction of GSTGs from MSC specifications. We propose action dependency graph as an intuitive description of semantics of MSC specifications and present an algorithm to translate MSC specifications to action dependency graphs as well as an algorithm to construct a global state transition graph from an action dependency graph.

This paper presents an efficient approach for a hardware/software partitioning problem: synthesis of an application-specific coprocessor which accelerates an embedded software running on a main processor. Given a set of data flow graphs (DFGs), most of previous hardware/software partitioning approaches have focused on mapping DFGs to hardware or software. Their common weaknesses are that 1) they ignore various implementation alternatives in realizing DFGs as hardware based on the assumption that only a single hardware implementation exists for a DFG, and that 2) they don't consider the effect of merging on hardware area when synthesizing a coprocessor by merging DFGs. To deal with the first issue, we formulate both the mapping of DFGs to hardware or software and the selection of the appropriate hardware implementation for each DFG as a single integer programming problem, and then apply an iterative algorithm based on the Kernighan and Lin's heuristic to solve the problem. To reduce the CPU time, we have devised data structures that quickly calculate costs of hardware implementations. To deal with the second issue, our method links DFGs with dummy nodes to produce a single large DFG, and then synthesizes a target coprocessor by globally scheduling the DFG and allocating its datapath. Experimental results demonstrate that our approach outperforms the previous approach based on genetic algorithm (GA) in both the coprocessor area and the CPU time.

This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.

This paper proposes a statistical method to estimate the optimal software release time which minimizes the expected total software cost incurred in both testing and operation phases. It is shown that the underlying cost minimization problem can be reduced to a graphical one. This implies that the software release problem under consideration is essentially equivalent to a time series forecasting for the software fault-occurrence time data. In order to predict the future fault-occurrence time, we apply three extraordinary auto-regressive models by Singpurwalla and Soyer (1985) as the prediction devices as well as the well-known AR and ARIMA models. Numerical examples are devoted to illustrate the predictive performance for the proposed method. We compare it with the classical exponential software reliability growth model based on the non-homogeneous Poisson process, using actual software fault-occurrence time data.

In the beginning of the new century, many information appliance (IA) products will replace traditional electronic appliances to help people in smart, efficient, and low-cost ways. These successful products must be capable of communicating multimedia information, which is embedded into the electronic appliances with high integration, innovation, and power-throughput tradeoff. In this paper, we develop a codesign procedure to analyze, compare, and emulate the multimedia communication applications to find the candidate implementations under different criteria. The experimental results demonstrate that in general, memory technology dominates the optimal tradeoff and ALU improvements impact greatly on particular applications. The results also show that the proposed procedure is effective and quite efficient.

Most of current codesign tools or methodologies only support validation in the form of cosimulation and testing of design alternatives. The results of hardware-software codesign of a distributed system are often not verified, because they are not easily verifiable. In this paper, we propose a new formal coverification approach based on linear hybrid automata, and an algorithm for automatically converting codesign results to the linear hybrid automata framework. Our coverification approach allows automatic verification of real-time constraints such as hard deadlines. Another advantage is that the proposed approach is suitable for verifying distributed systems with arbitrary communication patterns and system architecture. The feasibility of our approach is demonstrated through several application examples. The proposed approach has also been successfully used in verifying deadline violations when there are inter-task communications between tasks with different period lengths.

This paper first examines the issues related to scheduling loop applications on a software distributed shared memory (DSM) system. Then, a dynamic scheduling scheme is developed based on the examined issues to enhance the performance of loop applications on DSM. Compared with previous works, the proposed scheme has several specialties. The first is that the workload of processors can be effectively balanced even when the computational capabilities of processors and the computational needs of threads are not identical. The second is it divides thread mapping into two phases, each with one consideration, i.e., load balance or communication cost, and adopts thread migration and exchange in the two phases, respectively. The third is the exploitation of data sharing among threads to reduce data-consistency communication, and the last is to attack the negative effect of the unnecessary inter-node sharing caused by thread re-mapping. The proposed scheme has been implemented on a page-based DSM system called Cohesion. Our experiments show that the proposed scheme is more effective to improve the performance of the test programs than related schemes.

This letter empirically evaluates the way how to calculate the complexity of methods, that is used in the definition of WMC(Weighted Method per Class), one of the Chidamber and Kemerer's metrics. With respect to the results of our experiment, Halstead's Software Science metric is the most appropriate one to evaluate the complexity of the methods.

The use of intelligent agents is on the rise, fueled by the unprecedented growth in the Internet and web based applications. Consequently, agent-oriented software is becoming large and complex. To support a systematic development of such software, an agent-oriented software development methodology is necessary. This paper focuses on the modeling phase of agent-oriented software life cycle and, presents an approach for agent modeling consisting of Agent Elicitation, Intra, and Inter Agent modeling methods. Agent Elicitation deals with identifying and extracting agents from "classes" in the real world. Intra Agent Modeling involves expressing agent characteristics - Goal, Belief, Plan and Capability - whereas, Inter Agent modeling incorporates agent mobility and communication in a multi-agent system.

I describe a software reliability growth model that yields accurate parameter estimates even with a small amount of input data. The model is based on a proposed discrete analog of a Gompertz equation that has an exact solution. The difference equation tends to a differential equation on which the Gompertz curve model is defined, when the time interval tends to zero. The exact solution also tends to the exact solution of the differential equation when the time interval tends to zero. The discrete model conserves the characteristics of the Gompertz model because the difference equation has an exact solution. Therefore, the proposed model provides accurate parameter estimates, making it possible to predict in the early test phase when software can be released.

This paper presents the results on IF/baseband up/down direct digital conversion and multiple channel analysis/synthesis software defined radio modules which are implemented using high speed ADC, DAC and FPGA, for IS-95 code division multiple access (CDMA) systems. The implemented system can directly down-convert multiple channel IS-95 CDMA IF signals to the baseband, and selectively analyze specific channel signals based on polyphase analysis filter bank techniques. Moreover, the analyzed baseband signals of multiple channels can be directly up-converted and synthesized in the same system. We have deployed the implemented system in IS-95 CDMA optical digital repeaters for PCS applications.

Interference suppression is one of the important functions for mobile communications and software radio. First, this paper shows a new type of interference suppression method by P-RCE (Probability-Restricted Coulomb Energy) which is applicable to mobile communications and software radio. P-RCE is one of the neural networks and mainly used in the field of pattern classification. Secondly, this paper presents several characteristics of this method. For example, it is found from our studies that good suppression effects can be performed even when the interference signals exist closely adjacent to the desired signal and/or total number of signals is more than that of the antenna elements. Next, this paper discusses two types of improvement of processing speed for new suppression method. One is the setting up the learning and non-learning intervals, and the other is the restriction of the number of prototype cells. According to the results, fairly good improvement is realized.