There are the following three targets to be achieved in a software project from the three viewpoints of process management (or progress management), cost management, and quality management for software project to be successful: (a) drafting a software development plan based on accurate estimation, (b) early detection of risks that the project includes based on correct situation appraisal, (c) early avoidance of risks that the project includes. In this paper, the authors propose a method and facilities to project risks in a software project through Kepner-Tregoe program, and propose schedule re-planning by using genetic algorithm for avoiding the projected risks. Furthermore the authors show, from the results of execution of the system, that the system is effective in early avoidance of risks that the software project includes.

The quality of an architectural design of a software system has a great influence on achieving non-functional requirements to the system, so formal evaluation and validation techniques to designed architectures are necessary in the early phase of development processes. In this paper, we present a technique for describing software architectures formally based on Coloured Petri Nets (CPNs) and a technique for reusing architectural constituents. Architectural descriptions are essentially written with a CPN language, so that the evaluation and analysis on the architectural descriptions can be made in architectural design phrase. We extract reusable architectural parts from standard architecture styles and architectural patterns so that a designer can construct an architecture by only retrieving the parts and combine them. We also designed the language for describing the combination of the architectural parts. To show the effectiveness of our techniques, we illustrate how a blackboard architecture can be composed of reusable parts and be simulated on a CPN tool (Design/CPN).

This paper discusses a framework for automating fault management using distributed software agents. The management function is distributed among multiple agents that can carry out advanced reasoning activities on the network domain. Network domain modeling using Bayesian network is introduced. The agent detects, correlates and selectively seeks to derive a clear explanation of the alarms generated in its domain. Depending on the network's degree of automation, the agent can even carry out local recovery actions. The ideas of the paper are implemented in a software for inference in Bayesian network. We identify the potentialities of learning in the agent model, and present the class of problems to be addressed.

The Capability Maturity Model (CMM) proposed by the Software Engineering Institute (SEI) of Carnegie Mellon University (CMU) is an effective framework for software process improvement (SPI) because it can increase development productivity and improve software quality for many software development companies. However, the CMM only indicates 'what' needs to be improved, it does not indicate 'how to' perform software process improvement activities (SPIA). In this paper we describe a Software Process Improvement support System (SPIS) that does indicate 'how to' perform SPIA. It is designed to be used mainly for internal SPIA by software development companies and their project teams. The SPIS is composed of seven support tools and promotes SPIA. The tools include a specific capability maturity model (SCMM), rules for assessing a company's maturity level, and an assessor qualification system for organizing the assessment team. These tools were extracted deductively from our experience and have proved to be effective when used for the SPIA at our company. (R): CMM is registered trademarks in the U. S. Patent and Trademark Office. SM: CMM is a service mark of Carnegie Mellon University.

This paper discusses the characteristics of human design knowledge. By studying a number of actual human made designs of excellent designers, the most frequent basic mental operations of a typical human designer have been found. They are: a design rule for hierarchical detailing reported previously, a micro design rule for generating a hierarchical expansion, dictionary operations to build a micro design rule and dictionaries. This study assumes a multiplicity of knowledge based on Zipf's theory, "the principle of least effort. " Zipf's principle may be proved and it becomes possible to understand the fundamental nature of human design.

This paper presents a model for the naming, packing, version control, storage, and retrieval of software assets. The naming and version control schemes are based on content-derived coding of the asset body. The name-to-asset mapping can be fixed or be varying with time. The packing scheme is designed so that the asset integrity verification and authentication information is made an intrinsic part of the packed asset. A comparison with an existing naming and version control scheme is given. The storage and retrieval scheme is a unification of four most commonly used methods, namely the enumerative method, the keyword-based method, the faceted method, and the text-based method. This unification makes it possible for the users to access heterogeneous repositories (with different storage and retrieval methods) simultaneously, using the same tool set and query syntax. The degradation functions technique is used to automatically broaden queries. A demonstrative retrieval tool is described to show how the unification of methods is done at the user interface level.

In digital signal processing, bit width of intermediate variables should be longer than that of input and output variables in order to execute intermediate operations with high precision. Then a processor core for digital signal processing is required to have two types of register files, one of which is used by input and output variables and the other one is used by intermediate variables. This paper proposes a hardware/software cosynthesis system for digital signal processor cores with two types of register files. Given an application program and its data, the system synthesizes a hardware description of a processor core, an object code running on the processor core, and software environments. A synthesized processor core can be composed of a processor kernel, multiple data memory buses, hardware loop units, addressing units, and multiple functional units. Furthermore it can have two types of register files RF1 and RF2. The bit width and number of registers in RF1 or RF2 will be determined based on a given application program. Thus a synthesized processor core will have small area with keeping high precision of intermediate operations compared with a processor core with only one register file. The experimental results demonstrate the effectiveness of the proposed system.

Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.

This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

Multimedia mobile communication systems are expected to be realized in the near future. In such systems, multipath fading can cause severe degradations of the quality of the communications due to its wide bandwidth, especially in urban areas. Adaptive array antennas can be attractive solution for overcoming the multipath fading. Suppression can be achieved with the adaptive array by cophasing and combining multipath signals in the space and time domain. On the other hand, the concept of software antenna has been proposed. The software antenna recognizes radiowave environments and appropriately reconfigures itself for the signal processing required by the recognized environment. Efficient implementations can be expected if these functions are realized by the software. In this paper, we propose two types of the adaptive array systems which is reconfigurable depending on the radiowave environment as a realization of the concept of the software antenna. They recognize the environment by using the eigenvalue decomposition of space domain correlation matrices and reconfigure their structures of the signal processing. The principle and performance are examined by theoretical means and through computer simulations.

Adaptability evaluation of software systems is one of the key concerns in both software engineering and requirements engineering. In this paper, we present a formal and systematic approach to evaluate adaptability of software systems to requirements in enterprise business applications. Our approach consists of three major parts, that is, the common modeling method for both business realms and software realms, functional adaptability evaluation between the models with Σ algebra and behavioral adaptability evaluation with process algebra. By our approach, one can rigorously and uniquely determine whether a software system is adaptable to the requirements, either totally or partially. A sample application from an order processing is illustrated to show how this approach is effective in solving the adaptability evolution problem.

In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.

In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel, multiple data memory buses (X-bus and Y-bus), hardware loop units, addressing units, and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data, the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.

In order to lead an ongoing software project to success, it is important to flexibly control its dynamically-changing software process. However, it is generally impossible not only to exactly pre-define the production process but also to prescribe the process change process (meta-process). To solve the problem, we have focused on communication between the project staff through which process change requests presented by individuals can be immediately shared, designed, verified, validated and implemented. This paper proposes a communication model which can represent a wide variety of communication states between the project manager and developers discussing how to implement process change requests. The communication model has been derived by investigating the sort of process change requests and, based on the model, we have implemented a cooperative process planning system (called CooPs). CooPs is a communication environment designed for software projects and supports information sharing for discussing the process change requests. By using CooPs, the software project can flexibly deal with not only expected change requests but also unexpected ones. To evaluate the applicability of the communication model and the capabilities of CooPs, we have conducted an experiment which is an application of CooPs to the ISPW6 example problem. This paper describes the concepts of CooPs, the system implementation, and the experiment.

A software system has dynamic adaptability if it can adapt itself to dynamically changing runtime environments. As open-ended distributed systems and mobile computing systems have spread widely, the need for software systems with dynamic adaptability increases. We propose a software model with dynamic adaptability called DAS and its description language LEAD++. The basic mechanism for dynamic adaptability is called adaptable procedure. An adaptable procedure is a special kind of generic procedures (functions) whose methods are selected based upon the state of its runtime environment. Furthermore, control mechanisms of adaptable procedures -- including method selection strategies -- are realized using generic procedures. This sort of reflective architecture enables us to write a dynamically adaptable software system in highly flexible, extensible, readable and maintainable way. LEAD++ is an object-oriented reflective language that provides adaptable procedures and their control mechanisms as its basic language functionalities. We are currently implementing a prototype of LEAD++ as a pre-processor of Java. Using LEAD++, we can systematically describe dynamically adaptable applets, mobile objects, etc.

The intermediate language (IL) modularizes a compiler into target processor independent and dependent parts, called the front-end and the back-end. By adding a new back-end, it is possible to port existing software from one processor to another. This paper presents a new efficient approach to achieve multiple targeting to quite different architectures using different processors as well, by translating from one IL into other existing ILs. This approach makes it possible to reuse existing back-ends. It has been successfully applied to a commercial-scale project for porting public switching system software. Since the target ILs were not predictable in advance, we provided an abstract syntax tree (AST) with attributes accessible by abstract data type (ADT) interface to convey the source language information from our front-end to back-ends. It was translated into several ILs that were developed independently. These translations made the compiler available in a very short time for different cross-target platforms and on several workstations we needed. The structure of this AST and the mapping to these ILs are presented, and retargeting cost is evaluated.

The paper investigates several approaches for designing and implementing integration environments. Such an environment is developed for the purpose to allow cooperative interactions between distributed and heterogeneous systems. A possible approach to achieve system integration is to use the warehousing technology which engenders the development of data warehousing environments. These environments are information repositories that are available for queries and analysis. In order to manage efficiently a data warehouse, software agents enhanced with mobility mechanisms are introduced. A software agent is an autonomous entity having the abilities to collaborate with each other and to answer users' needs. Furthermore, to perform their operations software agents can migrate off their hosts and roam the network to gather relevant information. This research is part of the SAMDW project which aims at developing a new generation of data warehouses.

In this paper, we show two methods for fast software implementations of block cipher algorithm MISTY1 on Digital Alpha processors. One is based on the method proposed by Biham at the fourth Fast Software Encryption Workshop. This method, which is called "bitslice," realizes high performance by regarding the target cipher as a collection of logic gates and processing plural blocks in parallel, although its data format is non-standard. The other is standard implementation where all modes of operation are available. We analyze the architecture of Alpha and discuss how to optimize MISTY1 on the processor. As a result, our assembly language programs achieved an encryption speed of 288 Mbps for the bitslice version and 105 Mbps for the standard version, respectively, on Alpha 21164A (500 MHz).

The software requirements specification process consists of three steps; requirements capture and analysis, requirements definition and specification, and requirements validation. At the beginning of the second step which this paper focuses on, there have been several types of massive documents generated in the first step. Since the developers and the clients/users of the new software system may not have common knowledge in the field which the system deals with, it is difficult for the developers to produce correct requirements specification by using these documents. There has been few research work to solve this problem. The authors have developed a support tool to produce correct requirements specification by arranging and restructuring those documents into clearly understandable forms. In the second step, the developers must specify the functions and their constraints of the new system from those documents. Analyzing the developers' real activities for designing the support tool, the authors propose a model of this step as the following four activities. To specify the functions of the new system, the developers must collect the sentences which may suggest the functions scattering those documents. To define the details of each function, the developers must gather the paragraphs including the descriptions of the functions. To verify the correctness of each function, the developers must survey all related documents. To perform above activities successfully, the developers must manage various versions of those documents correctly. According to these four types of activities, the authors propose the effective ways to support the developers by arranging those documents. This paper shows algorithms based on this model by using the structures of the documents and keywords which may suggest the functions or constraints. To examine the feasibility of their proposal, the authors implemented a prototype tool. Their tool extracts complete information scattering those documents. The effectiveness of their proposal is demonstrated by their experiments.