We propose the kernel-based pattern recognition hardware and its design methodology using the genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.

We examine diagnosis of processor array systems formed as two-dimensional grids, with boundaries, and either four or eight neighbors for each interior processor. We employ a parallel test schedule. Neighboring processors test each other and report the results. Our diagnostic objective is to find a fault-free processor or set of processors. The system may then be sequentially diagnosed by repairing those processors tested faulty according to the identified fault-free set. We establish an upper bound on the maximum number of faults that can be sustained without invalidating the test results under worst case conditions. We give test schedules and diagnostic algorithms that meet the upper bound as far as the highest order term. We compare these near optimal diagnostic algorithms to alternative algorithms--both new and already in the literature.

In this paper, we study nonblocking supervisory control of discrete event systems under partial observation. We introduce a weak normality condition defined in terms of a modified natural projection map. The weak normality condition is weaker than the original one and stronger than the observability condition. Moreover, it is preserved under union. Given a marked language specification, we present a procedure for computing the supremal sublanguage which satisfies Lm(G)-closure, controllability, and weak normality. There exists a nonblocking supervisor for this supremal sublanguage. Such a supervisor is more permissive than the one which achieves the supremal Lm(G)-closed, controllable, and normal sublanguage.

Turbo coding is widely known as one of effective error control coding techniques in various digital communication systems since this coding method has proposed by C. Berrou, etc in 1993. In digital magnetic recording, it has been cleared that the error correcting capability of turbo coding is superior to most of conventional recording codes as a matter of course. But, the performance of a partial response maximum-likelihood (PRML) system combined with any recording code is degraded by many undesirable factors or effects. To improve the performance of the PRML system in high areal density recording, it is useful to adopt a higher order PRML system or high rate code in a general case. In this paper, the rate 32/34 turbo code combined with an enhanced extended class-4 partial response (E2PR4) is proposed. We call this trellis coded partial response (TCPR) system the rate 32/34 turbo-coded E2PR4 (32/34 TC-E2PR4). Our proposed TCPR system can be expected to get large coding gain and improve the performance of PRML system. As a result, the proposed coding system provides a good performance compared with the conventional systems. In especial, our system can achieve a BER of 10-5 with SNR of approximately 1.5 dB less than the conventional 8/9 maximum transition run (MTR) coded E2PR4ML system at a normalized linear density of 3.

In an optical fiber ring topology network such as FDDI (Fiber Distributed Data Interface) rings and SONET (Synchronous Optical Network) rings, the number of consecutively bypassed failed stations is limited by the optical power loss constraint. In recent years, this situation was represented as a consecutive k-out-of-n:F system and the two-terminal reliability was presented in the literature, but K-terminal reliability has not been presented. In this paper, we obtain K-terminal reliability expressions for dual-counter rotating networks (DR's) that use both self-heal and station-bypass switches in which all components (stations, links and bypass switches) can fail. The results are useful in evaluating the reliabilities of FDDI ring networks parametrically and making reliability comparisons. This method can be used to obtain a closed-form reliability expression in a more general ring-network such as 'ring of trees. '

Distributed domino effect-free checkpointing techniques can be divided into two categories: coordinated and communication-induced checkpointing. The former is inappropriate for mobile computing systems because it either forces every mobile host to take a new checkpoint or blocks the underlying computation during the checkpointing process. The latter makes every mobile host take the checkpoint independently. However, each mobile host may need to store multiple local checkpoints in stable storage. This investigation presents a novel three level synchronous checkpointing algorithm that combines the advantages of above two methods for mobile computing systems. The algorithm utilizes pre-synchronization, quasi-synchronization, and post-synchronization techniques and has the following merits: (1) Consistent global checkpoints can be ensured. (2) No mobile host is blocked during checkpointing. (3) Only twice the checkpoint size is required. (4) Power consumption is low. (5) The disconnection problem of mobile hosts can be resolved. (6) Very few mobile hosts in doze mode are disturbed. (7) It is simple and easy to implement. The proposed algorithm's numerical results are also provided in this work for comparison. The comparison reveals that our algorithm outperforms other algorithms in terms of checkpoint overhead, maintained checkpoints, power consumption, and disturbed mobile hosts.

A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.

In this paper, a design of Programmable Logic Device (PLD) and a synthesis approach are proposed. Our PLD is derived from traditional Programmable Logic Array (PLA). The key extension is that programmable AND devices in PLA is replaced by Look-Up Tables (LUTs). A series of cascaded LUTs in the array can generate more complex terms, which we call generalized complex terms (GCTs), than product terms. In order to utilize the capability, a synthesis approach to map a given function into the array is also proposed. Our approach generates a expression of the sum of GCTs aiming to minimize the number of terms. A number of experimental results demonstrate that the number of terms for our PLD generated by our approach is 14.9% fewer than that by an existing approach. We design our PLD based on a fundamental unit named nGCT cell which can be used as LUTs in multiple sizes or random access memories. Implementation of the PLD based on a fundamental unit named nGCT cell which can be used as LUTs or random access memories is also described.

Agent technology is widely recognized as a new paradigm for the design of concurrent software and systems. The aim of this paper is to give a mathematical foundation for the design and the analysis of multi-agent systems by means of a Petri-net-based model. The proposed model, called PN2, is based on place/transition nets (P/T nets), which is one of the simplest classes of Petri nets. The main difference of PN2's from P/T nets is that each token, representing an agent, is also a P/T net. PN2's are sufficiently simple for the mathematical analysis, such as invariant analysis, but have enough modeling power.

Petri net is a mathematical model for concurrent systems. Liveness is one of important properties of Petri net. Liveness problem of general Petri net is of exponential space complexity and subclasses are suggested with less computational complexity. It is well known that liveness problem of bounded (extended) free choice net is solved in deterministic polynomial time. This paper treats liveness problem of AC/DC nets. AC/DC net is a subclass of Petri net that exhibits no confusion (mixture of concurrency and conflict). This class properly includes the class of free choice nets. It is shown that every minimal siphon of an AC/DC net is trap if and only if every strongly connected siphon is a trap. This result shows that monotone liveness of bounded AC/DC net is solved in deterministic polynomial time. It is shown that this result is true of bounded time AC/DC net with static fair condition.

This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.

In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.

Over recent years, "Internet-able" applications and architectures have been used to support domains where there are multiple interconnected systems that are both decentralized and autonomous. In enterprise-level data management domains, both the schema of the data repository and the individual query needs of the users evolve over time. To handle this evolution, the resulting architecture must enforce the autonomy in systems that support the client needs and constraints, in addition to maintaining the autonomy in systems that support the actual data schema and extraction mechanisms. At the MITRE Corporation, this domain has been identified in the development of a composite data repository for the Center for Advanced Aviation System Development (CAASD). In the development of such a repository, the supporting architecture includes specialized mechanisms to disseminate the data to a diverse evolving set of researchers. This paper presents the motivation and design of such an architecture to support these autonomous data extraction environments. This run-time configurable architecture is implemented using web-based technologies such as the Extensible Markup Language (XML), Java Servlets, Extensible Stylesheets (XSL), and a relational database management system (RDBMS).

The imprecise computation is one of the promising schemes in the real time systems to adapt quality of computations to change of load with keeping the deadlines of tasks in the systems. When overload occurs in the systems, the minimum requirements on the deadline are assured by decreasing quality of the computation. This paper describes how to apply the concept of the imprecise computation to automobile control in the expressway assuming the intelligent transportation system (shortly, ITS). The deadline violation of tasks for automobile control in the expressway induces collision of automobiles. Regardless of whether the expressway is congested or not, collision of automobiles must be avoided. To satisfy such requirement, the concept of the imprecise computation is effective. This paper proposes an adaptive scheduling using the imprecise computation to avoid collision of automobiles and increase throughput, and shows results of simulation experiments about an adaptive scheduling for automobiles control.

In this paper, we propose an approach to solve the power control issue in a DS-CDMA cellular system using genetic algorithms (GAs). The transmitter power control developed in this paper has been proven to be efficient to control co-channel interference, to increase bandwidth utilization and to balance the comprehensive services that are sharing among all the mobiles with attaining a common signal-to-interference ratio(SIR). Most of the previous studies have assumed that the transmitter power level is controlled in a constant domain under the assumption of uniform distribution of users in the coverage area or in a continuous domain. In this paper, the optimal centralized power control (CPC) vector is characterized and its optimal solution for CPC is presented using GAs in a large-scale DS-CDMA cellular system under the realistic context that means random allocation of active users in the entire coverage area. Emphasis is put on the balance of services and convergence rate by using GAs.

Recently, Kasahara and Murakami proposed new product-sum public-key cryptosystems using the Chinese remainder theorem as the trapdoor. We proposed 'Yaezakura' as the high-density product-sum PKC applying the method using the reduced bases. In this paper, we propose another high-density scheme with the Chinese remainder theorem trapdoor using the message extension. We also show that the proposed scheme is invulnerable to the low-density attack. In the proposed scheme, the sender can freely select the positions of the dummy messages.

There is an ever-increasing demand for better performance and scalability in workflow systems. We describe how mobile agents can be used to satisfy such a requirement. For the purpose two important design issues are pointed out in workflow execution and architecture levels. Agent delegation models and a 3-layer architecture are suggested in mobile agent based workflow systems as a solution for each consideration. Workload is statically distributed over task performers based on the proposed method. As a result the performance and the scalability are improved. The effectiveness is shown through stochastic Petri-nets simulation through comparison with client-server based- and another mobile agent-based workflow systems.

Autonomous Information Service System is a proposition made to cope with the continuously changing conditions of service provision and utilization in current information systems. The faded information field (FIF), sustained by push/pull mobile agent technology, is such a distributed architecture that brings high-assurance of the system through a balanced selective replication of the information. When the demand changes, the information environment is restructured so that the same response time to services for all unspecified users can be achieved whatever the demand volume. However, once the structure is fixed, dispatching the randomly incoming requests on the FIF is still required to guarantee the same quality of service. Our goal is to warrant the autonomous dispatching of the pull mobile agents to adjust the continuously evolving arrival distribution of the demand to the current information environment. In this paper, we explain the concepts and realization of autonomous navigation under the goal of an autonomous load balancing of the pull mobile agent volume in the FIF structure. The appropriateness of this method for FIF environments has been shown by simulation.

A new architecture and methods for an enhanced autonomous decentralized production system (EADPS) are described. This EADPS was developed to ensure high flexibility of production systems consisting of intelligent devices based on the autonomous decentralized system model and to guarantee the time used for communication to simultaneously maintain high productivity. The system architecture of the EADPS guarantees the time by managing groups of nodes and the priorities in these groups. A bit-arbitration method is used to prevent collision of messages. The nodes autonomously check the waveforms in the network and terminate transmission when the nodes with a higher priority are transmitting. A parallel-filtering method is used to speed up message acceptance. The nodes check the identifiers of the messages using parallel-filtering circuits and each node determines autonomously where a message should be accepted or not. Implementing the system architecture and these methods as circuits and integrating the circuits into a chip using system LSI technologies resulted in low-cost implementation of the system. Experimental evaluation demonstrated the effectiveness of this system.

System needs of growing systems including heterogeneous functions and operations are increased. High assurance system that achieves high reliability and high availability is very important for such systems. In order to realize high assurance system, we developed the assurance technology based on ADS (Autonomous Decentralized System). When a growing system changes or grows, its reliability may be lowered. In this paper, we clarify the risk factors which lower the reliability and quality of a growing system when the system is modified. We will then examine the technology to eliminate or mitigate those risk factors, and propose adaptive assurance technology that can minimize the risk. We also applied this technology to ATOS for Tokyo Metropolitan Railway Network as an example of really changing and growing system and mention its effectiveness. ATOS; Autonomous Decentralized Transport Operation Control System.