Sophisticated and robust resource management is an essential issue in future wireless systems which will provide a variety of application services. In this paper, we employ an adaptive-network-based fuzzy inference system (ANFIS) to control the resource allocation for mobile multimedia networks. ANFIS, possessing the advantages of expert knowledge of fuzzy logic system and learning capability of neural networks, can provide a systematic approach to finding appropriate parameters for the Sugeno fuzzy model. The fuzzy resource allocation controller (FRAC) is designed in a two-layer architecture and selects properly the capacity requirement of new call request, the capacity reservation for future handoffs, and the air interface performance as input linguistic variables. Therefore, the statistical multiplexing gain of mobile multimedia networks can be maximized in the FRAC. Simulation results indicate that the proposed FRAC can keep the handoff call blocking rate low without jeopardizing the new call blocking rate. Also, the FRAC can indeed guarantee quality of service (QoS) contracts and achieve higher system performance according to network dynamics, compared with the guard channel scheme and ExpectedMax strategy.

An LSI has been fabricated and measured to demonstrate feasibility of VDD-hopping scheme in an embedded system level by executing MPEG4 CODEC. In the VDD-hopping, supply voltage of a processor is dynamically controlled by a hardware-software cooperative mechanism depending on workload of the processor. When the workload is about a half, the VDD-hopping is shown to reduce power to less than a quarter compared to the conventional fixed-VDD scheme. The power saving is achieved without degrading real-time features of MPEG4 CODEC.

Almost all of the current public-key cryptosystems (PKCs) are based on number theory, such as the integer factoring problem and the discrete logarithm problem (which will be solved in polynomial-time after the emergence of quantum computers). While the McEliece PKC is based on another theory, i.e. coding theory, it is vulnerable against several practical attacks. In this paper, we summarize currently known attacks to the McEliece PKC, and then point out that, without any decryption oracles or any partial knowledge on the plaintext of the challenge ciphertext, no polynomial-time algorithm is known for inverting the McEliece PKC whose parameters are carefully chosen. Under the assumption that this inverting problem is hard, we propose a slightly modified version of McEliece PKC that can be proven, in the random oracle model, to be semantically secure against adaptive chosen-ciphertext attacks. Our conversion can achieve the reduction of the redundant data down to 1/3-1/4 compared with the generic conversions for practical parameters.

For several years, more and more people are joining the Internet and various kind of packets (so called transaction-, block-, and stream-types) have been transmitted in the same network, so that poor network conditions cause loss of the stream-type data packets, such as voices, which request smaller transmission delay time than others. We consider a switching node (router) in a network as an N-series M/G/1-type queueing model and have mainly evaluated the fluctuation of packet delay time and end-to-end delay time, using the two moments matching method with initial value, then define the delay jitter D of a network which consists of jointed N switching nodes. It is clarified that this network is not suitable for voice packets transmission media without measures.

In this paper, a design method of neural-net based PID controllers is proposed for multivariable nonlinear systems with mutual interactions. The proposed method adopt both a static pre-compensator and some multi-layered neural networks. The former is used for roughly decoupling the controlled object, and the latter is used in order to improve decoupling and to linearize the approximately decoupled controlled object. Also the design scheme based on the relationship between PID law and the generalized minimum variance control (GMVC) law is adopted. The effectivenes of the proposed control scheme is evaluated on a simulation example.

We present a scalar multiplication algorithm with recovery of the y-coordinate on a Montgomery-form elliptic curve over any non-binary field. The previous algorithms for scalar multiplication on a Montgomery form do not consider how to recover the y-coordinate. So although they can be applicable to certain restricted schemes (e.g. ECDH and ECDSA-S), some schemes (e.g. ECDSA-V and MQV) require scalar multiplication with recovery of the y-coordinate. We compare our proposed scalar multiplication algorithm with the traditional scalar multiplication algorithms (including Window-methods on the Weierstrass form), and discuss the Montgomery form versus the Weierstrass form in the performance of implementation with several techniques of elliptic curve cryptosystems (including ECES, ECDSA, and ECMQV). Our results clarify the advantage of the cryptographic usage of Montgomery-form elliptic curve in constrained environments such as mobile devices and smart cards.

The smart vision chip has a large potential for application in general purpose high speed image processing systems. In order to fabricate smart vision chips including photo detector compactly, we have proposed the application of three dimensional LSI technology for smart vision chips. Three dimensional technology has great potential to realize new biologically inspired systems inspired by not only the biological function but also the biological structure. In this paper, we describe our three dimensional LSI technology for biologically inspired circuits and the design of smart vision chips.

This paper describes the adaptability of communication software through a biologically-inspired policy coordination. Many research efforts have developed adaptable systems that allow various users or applications to meet their specific requirements by configuring different design and optimization policies. Navigating through many policies manually, however, is tedious and error-prone. Developers face the significant manual and ad-hoc work of engineering an system. In contrast, we propose to provide autonomous adaptability in communication endsystem with OpenWebServer/iNexus, which is both a web server and an object-oriented framework to tailer various web services and applications. The OpenWebServer's modular architecture allows to abstract and maintain a wide range of aspects in a HTTP server, and reconfigure the system by adding, deleting, changing, or replacing their policies. iNexus is a tool for automated policy-based management of OpenWebServer. Its design is inspired by the natural immune system, particularly immune network, a truly autonomous decentralized system. iNexus inspects the current system condition of OpenWebServer periodically, measures the delivered quality of service, and selects suitable set of policies to reconfigure the system dynamically by relaxing constraints between them. The policy coordination process is performed through decentralized interactions among policies without a single point of control, as the natural immune system does. This paper discusses communication software can evolve continuously in the piecemeal way with biological concepts and mechanisms, adapting itself to ever-changing environment.

In this paper, we describe a frame synchronization method for bi-orthogonal modulation systems. In bi-orthogonal modulation systems, several bi-orthogonal sequences are used for data transmission. Frame synchronization in bi-orthogonal modulation systems is difficult because transmitted sequences can change every frame. In the proposed method, each bi-orthogonal sequence consists of two different inner sequences. Each bi-orthogonal sequence has the same arrangement of two different inner sequences. A receiver can track the frame timing by observing the arrangement of inner sequences. In this paper, we analyze the bit error rate performance that takes into account the tracking performance of a system we developed based on our method. The spectral efficiency of the proposed system in code division multiple access (CDMA) systems is also investigated. As a result, we found that the proposed system is effective in synchronous CDMA systems.

The packaging hierarchy is not fixed structure. It can be changed depending on the packaging technology itself, and the number of hierarchy levels tends to decrease. In LSI-package technology including package-to-board interconnections, there were two evolutionary changes. The first evolution was from PTH to SMT, and the second evolution was from "Peripheral connections" to "Area-array connections. " These evolutions have been caused by ICs integration and application products requirements. Now, the third evolution appears to be in progress, which is from SCP to MCP or SIP. Although SoC has many remarkable features, it has been not applied for many systems contrary to expectations, and its limitations or issues have become clear. SIP is the answer for above SoC's issues. MCP can be considered to be primitive SIP. The purpose of MCP is making up the technology gap between SMT and SoC to address the issues. The targets of SIP are mainly the next two items. (1) Overcoming the interconnection crisis of SoC. (2) Opening new application fields in electronics. In order to achieve those targets, several consortiums in the world are doing research and developing core technologies.

Functional magnetic resonance imaging (fMRI) allows to display functional activities of certain brain areas. In combination with a three dimensional anatomical dataset, acquired with a standard magnetic resonance (MR) scanner, it can be used to identify eloquent brain areas, resulting in so-called functional neuronavigation, supporting the neurosurgeon while planning and performing the operation. But during the operation brain shift leads to an increasing inaccuracy of the navigation system. Intraoperative MR imaging is used to update the neuronavigation system with a new anatomical dataset. To preserve the advantages of functional neuronavigation, it is necessary to save the functional information. Since fMRI cannot be repeated intraoperatively with the unconscious patient easily we tried to solve this problem by means of image processing and pattern recognition algorithms. In this paper we present an automatic approach for transfering preoperative markers into an intraoperative 3-D dataset. In the first step the brains are segmented in both image sets which are then registered and aligned. Next, corresponding points are determined. These points are then used to determine the position of the markers by estimating the local influence of brain shift.

This paper presents an application-specific, heterogeneous multiprocessor synthesis system, named HeMPS, that combines a form of Evolutionary Computation known as Differential Evolution with a scheduling heuristic to search the design space efficiently. We demonstrate the effectiveness of our technique by comparing it to similar existing systems. The proposed strategy is shown to be faster than recent systems on large problems while providing equivalent or improved final solutions.

A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we introduce the 1(1/2)-track switch torus array by changing the connections in 1(1/2)-track switch mesh array, and we apply our approximate reconfiguration algorithm to the torus array. We describe the reconfiguration strategy for the 1(1/2)-track switch torus array and its realization using WSI, especially 3-dimensional realization. A hardware realization of the algorithm is proposed and simulation results about the array reliability are shown. These imply that a self-reconfigurable system with no host computer can be realized using our method, hence our method is effective in enhancing the run-time reliability as well as the fabrication-time yield of processor arrays.

Future electronic systems can not be built only with System-on-a-Chip (SoC), since many SoC issues have become evident. Relatively low yield due to the larger die size and the huge investment in developing the process to embed different kinds of technologies are some of the issues. Instead, superconnect technology is getting more important as a viable solution in building electronic systems. The superconnect connects separately built and tested chips not by the printed circuit board but rather directly to construct high-performance yet low-cost electronic systems and may use around 10 micron level design rules. System-in-a-Package and stacked chips using interposers are some realization of the superconnect. The superconnect will also be used to mitigate IR-drop problems and RC delay problems in global on-chip interconnect.

In this paper, we describe a method for estimating external camera parameters in real time. We investigated the effectiveness of this method for annotating real scenes with 3-D virtual objects on a wearable computer. The proposed method enables determining known natural feature points of objects through multiplied color histogram matching and template matching. This external-camera-parameter calculation method consists of three algorithms for PnP problems, and it uses each algorithm selectively. We implemented an experimental system based on our method on a wearable vision system. This experimental system can annotate real objects with 3D virtual objects by using the proposed method. The system was implemented in order to enable effective annotation in a mixed-reality environment on a wearable computing system. The system consists of an ultra small CCD camera set at the user's eye, an ultra small display, and a computer. This computer uses the proposed method to determine the camera parameters. It then renders virtual objects based on the camera parameters and synthesizes images on a display. The system works at 10 frames per second.

Recently a high-resolution image that has more than one million pixels is available easily. However, such an image requires much processing time and memory for an image understanding system. In this paper, we propose an integrated image understanding system of multi-resolution analysis and multi-agent-based architecture for high-resolution images. The system we propose in this paper has capability to treat with a high-resolution image effectively without much extra cost. We implemented an experimental system for images of indoor scenes.

Fiber-optic MEMS which is fabricated by combining direct photo-lithography of optical fiber and silicon micro-machining is proposed. Preliminary results of micro-machining of optical fiber and variable telecommunication devices are presented.

As a new category of the optical application system integrated with electronics, the opto-electronic information system (OEIS) is presented. Combination of the different characteristic technologies, optics and electronics, is expected to be useful for development of an effective and high-performance information systems. The properties of the optical technologies such as parallelism, high-speed, and large information capacity can be utilized for information processing. Even if some of the functions are emulated by the electronics, the optics give more effective solutions. To implement the OEIS, various optoelectronic devices and fabrication technologies are available including vertical cavity surface emitting lasers and spatial light modulators. There are two forms of system construction for the OEIS: an application of optics to an electronic-based system and the reversed form. As examples of the OEIS, the parallel matching architecture (PMA) and the thin observation module by bound optics (TOMBO) are presented. The PMA is an architecture of parallel computing system specified for global processing. This architecture shows a typical strategy to utilize the optical interconnection capability with flexibility of the electronic technology. The TOMBO presents possibility of morphological conversion using combination of the optical and electronic technologies. A compound-eye imaging system and post digital processing enable us to realize a very thin image capturing system. The issues related on development of the OEIS are proper usage of optics, effective fusion of the optical and electronic technologies, methodologies for system construction, fabrication supporting tools, and development of attractive demonstrators other than communication and interconnection fields.

In the present GHz-clock high-density LSI, a design of signal lines is getting so critical that the transmission line analysis should be introduced to signal line design. This leads to the complex design of line structure and i/o drivers including impedance matching. Our target is to implement a system-in-package (SiP) for software-defined-radio (SDR). The SiP operates up to 10 GHz, and requires a compact and high-density packaging technology with a simple signal wiring design. In this paper, we propose a new concept of 3-D multilayer-stacked SiP. The new 3-D packaging concept includes (1) design guideline for interconnection lengths, (2) bridging register circuits in LSI chips, (3) flip-chip microbump bonding technology of chips onto system-buildup printed wiring boards (PWB), (4) multilayer-stacked 3-D package of several sets of chips and PWB, and (5) 100-µm-diameter bumps at peripheral region of PWB as vertical via-bump bus lines. A critical interconnect length, in which interconnect wiring is treated as a conventional RC line, is discussed for wiring design. Both wiring lengths in LSI chips and that among chips corresponding to total thickness of vertical bus lines are designed to be shorter than the critical length. The key points of the 3-D package for GHz signal transfer are a delay guarantee due to limitation of line length and separation between local lines in a chip and a bus line among chips.

Distributed domino effect-free checkpointing techniques can be divided into two categories: coordinated and communication-induced checkpointing. The former is inappropriate for mobile computing systems because it either forces every mobile host to take a new checkpoint or blocks the underlying computation during the checkpointing process. The latter makes every mobile host take the checkpoint independently. However, each mobile host may need to store multiple local checkpoints in stable storage. This investigation presents a novel three level synchronous checkpointing algorithm that combines the advantages of above two methods for mobile computing systems. The algorithm utilizes pre-synchronization, quasi-synchronization, and post-synchronization techniques and has the following merits: (1) Consistent global checkpoints can be ensured. (2) No mobile host is blocked during checkpointing. (3) Only twice the checkpoint size is required. (4) Power consumption is low. (5) The disconnection problem of mobile hosts can be resolved. (6) Very few mobile hosts in doze mode are disturbed. (7) It is simple and easy to implement. The proposed algorithm's numerical results are also provided in this work for comparison. The comparison reveals that our algorithm outperforms other algorithms in terms of checkpoint overhead, maintained checkpoints, power consumption, and disturbed mobile hosts.