This paper presents a novel test data compression scheme for SoCs based on block merging and compatibility. The technique exploits the properties of compatibility and inverse compatibility between consecutive blocks, consecutive merged blocks, and two halves of the encoding merged block itself to encode the pre-computed test data. The decompression circuit is simple to be implemented and has advantage of test-independent. In addition, the proposed scheme is applicable for IP cores in SoCs since it compresses the test data without requiring any structural information of the circuit under test. Experimental results demonstrate that the proposed technique can achieve an average compression ratio up to 68.02% with significant low test application time.

In recent VLSIs, small-delay defects, which are hard to detect by traditional delay fault testing, can bring about serious issues such as short lifetime. To detect small-delay defects, on-chip delay measurement which measures the delay time of paths in the circuit under test (CUT) was proposed. However, this approach incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation. Our solution is a test application time reduction method for testing using the on-chip path delay measurement. The testing with on-chip path delay measurement does not require capture operations, unlike the conventional delay testing. Specifically, FFs keep the transition pattern of the test pattern pair sensitizing a path under measurement (PUM) (denoted as p) even after the measurement of p. The proposed method uses this characteristic. The proposed method reduces scan shift time and test data volume using test pattern merging. Evaluation results on ISCAS89 benchmark circuits indicate that the proposed method reduces the test application time by 6.89∼62.67% and test data volume by 46.39∼74.86%.

In this paper, we propose a hybrid test application in partial skewed-load (PSL) scan design. The PSL scan design in which some flip-flops (FFs) are controlled as skewed-load FFs and the others are controlled as broad-side FFs was proposed in [1]. We notice that the PSL scan design potentially has a capability of two test application modes: one is the broad-side test mode, and the other is the hybrid test mode which corresponds to the test application considered in [1]. According to this observation, we present a hybrid test application of the two test modes in the PSL scan design. In addition, we also address a way of skewed-load FF selection based on propagation dominance of FFs in order to take advantage of the hybrid test application. Experimental results for ITC'99 benchmark circuits show that the hybrid test application in the proposed PSL scan design can achieve higher fault coverage than the design based on the skewed-load FF selection [1] does.

This paper proposes the minimum transition random X-filling (MTR-fill) technique, which is a new X-filling method, to reduce the amount of power dissipation during scan-based testing. In order to model the amount of power dissipated during scan load/unload cycles, the total weighted transition metric (TWTM) is introduced, which is calculated by the sum of the weighted transitions in a scan-load of a test pattern and a scan-unload of a test response. The proposed MTR-fill is implemented by simulated annealing method. During the annealing process, the TWTM of a pair of test patterns and test responses are minimized. Simultaneously, the MTR-fill attempts to increase the randomness of test patterns in order to reduce the number of test patterns needed to achieve adequate fault coverage. The effectiveness of the proposed technique is shown through experiments for ISCAS'89 benchmark circuits.

This paper proposes a self-test method of coarse grain dynamically reconfigurable processors (DRPs) without hardware overhead. In the method, processor elements (PEs) compose a test frame, which consists of test pattern generators (TPGs), processor elements under test (PEUTs) and response analyzers (RAs), while testing themselves one another by changing test frames appropriately. We design several test frames with different structures, and discuss the relationship of the structures to the numbers of contexts and test frames for testing all the functions of PEs. A case study shows that there exists an optimal test frame which minimizes the test application time under a constraint.

Test compression / decompression scheme for reducing the test application time and memory requirement of an LSI tester has been proposed. In the scheme, the employed coding algorithms are tailored to a given test data, so that the tailored coding algorithm can highly compress the test data. However, these methods have some drawbacks, e.g., the coding algorithm is ineffective in extra test data except for the given test data. In this paper, we introduce an embedded decompressor that is reconfigurable according to coding algorithms and given test data. Its reconfigurability can overcome the drawbacks of conventional decompressors with keeping high compression ratio. Moreover, we propose an architecture of reconfigurable decompressors for four variable-length codings. In the proposed architecture, the common functions for four codings are implemented as fixed (or non-reconfigurable) components so as to reduce the configuration data, which is stored on an ATE and sent to a CUT. Experimental results show that (1) the configuration data size becomes reasonably small by reducing the configuration part of the decompressor, (2) the reconfigurable decompressor is effective for SoC testing in respect of the test data size, and (3) it can achieve an optimal compression of test data by Huffman coding.

Test compression / decompression using variable-length coding is an efficient method for reducing the test application cost, i.e., test application time and the size of the storage of an LSI tester. However, some coding techniques impose slow test application, and consequently a large test application time is required despite the high compression. In this paper, we clarify the fact that test application time depends on the compression ratio and the length of codewords and then propose a new Huffman-based coding method for achieving small test application time in a given test environment. The proposed coding method adjusts both of the compression ratio and the minimum length of the codewords to the test environment. Experimental results show that the proposed method can achieve small test application time while keeping high compression ratio.

LSI testing is critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-testability technique for LSI design and testing, there is a strong need to reduce the test data Volume, scan-in Power dissipation, and test application Time (VPT) of full-scan testing. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme to tackle all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3%, and 85.5% reduction effects in test data volume, average scan-in power dissipation, peak scan-in power dissipation, and test application time, respectively.

Test compression / decompression is an efficient method for reducing the test application cost. In this letter we propose a response compression method based on Huffman coding. The proposed method guarantees zero-aliasing and it is independent of the fault model and the structure of a circuit-under-test. Experimental results of the compression ratio and the size of the encoder for the proposed method are presented.

As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.

Full scan design of sequential circuits results in greatly reducing the cost of their test generation. However, it introduces the extra expense of many test clocks to control and observe the values of flip-flops because of the need to shift values for the flip-flops into the scan panh. In this paper we propose a new method of generating compact test sequences for scan-based sequential circuits on the assumption that the number of shift clocks is allowed to vary for each test vector. The method is based on Boolean function manipulation using a shared binary decision diagram (SBDD). Although the test generation algorithm is basically for general sequential circuits, the computational cost is much lower for scan-based sequential circuits than for non-scanbased sequential circuits because the length of a test sequence for each fault is limited. Experimental results show that, for all the tested circuits, test sequences generated by the method require much smaller number of test clocks than compact or minimum test sets for combinational logic part of scan-based sequential circuits. The reduction rate was 48% on the average in the experiments.