This paper presents an analysis of random number generators based on continuous-time chaotic oscillators. Two different methods for random number generation have been studied: 1) Regular sampling of a chaotic waveform, and 2) Chaotic sampling of a regular waveform. Kernel density estimation is used to analytically describe the distribution of chaotic state variables and the probability density function corresponding to the output bit stream. Random bit sequences are generated using analytical equations and results from numerical simulations. Applying the concepts of autocorrelation and approximate entropy, randomness quality of the generated bit sequences are assessed to analyze relationships between the frequencies of the regular and chaotic waveforms used in both random number generation methods. It is demonstrated that in both methods, there exists certain ratios between the frequencies of regular and chaotic signal at which the randomness of the output bit stream changes abruptly. Furthermore, both random number generation methods have been compared against their immunity to interference from external signals. Analysis shows that chaotic sampling of regular waveform method provides more robustness against interference compared to regular sampling of chaotic waveform method.

In recent years, much research interest has developed in image enhancement and haze removal techniques. With increasing demand for real time enhancement and haze removal, the need for efficient architecture incorporating both haze removal and enhancement is necessary. In this paper, we propose an architecture supporting both real-time Retinex-based image enhancement and haze removal, using a single module. Efficiently leveraging the similarity between Retinex-based image enhancement and haze removal algorithms, we have successfully proposed an architecture supporting both using a single module. The implementation results reveal that just 1% logic circuits overhead is required to support Retinex-based image enhancement in single mode and haze removal based on Retinex model. This reduction in computation complexity by using a single module reduces the processing and memory implications especially in mobile consumer electronics, as opposed to implementing them individually using different modules. Furthermore, we utilize image enhancement for transmission map estimation instead of soft matting, thereby avoiding further computation complexity which would affect our goal of realizing high frame-rate real time processing. Our FPGA implementation, operating at an optimum frequency of 125MHz with 5.67M total block memory bit size, supports WUXGA (1,920×1,200) 60fps as well as 1080p60 color input. Our proposed design is competitive with existing state-of-the-art designs. Our proposal is tailored to enhance consumer electronic such as on-board cameras, active surveillance intrusion detection systems, autonomous cars, mobile streaming systems and robotics with low processing and memory requirements.

This paper presents an interference suppression and signal restoration technique that can create the clean signals required by automotive frequency-modulated continuous wave radar systems. When a radar signal from another radar system interferes with own transmitted radar signal, the target detection performance is degraded. This is because the beat frequency corresponding to the target cannot be estimated owing to the increase in the noise floor. In this case, advanced weighted-envelope normalization or wavelet denoising can be used to mitigate the effect of the interference; however, these methods can also lead to the loss of the desired signal containing the range and velocity information of the target. Therefore, we propose a method based on an autoregressive model to restore a signal damaged by mutual interference. The method uses signals that are not influenced by the interference to restore the signal. In experiments conducted using two different automotive radar systems, our proposed method is demonstrated to effectively suppress the interference and restore the desired signal. As a result, the noise floor resulting from the mutual interference was lowered and the beat frequency corresponding to the desired target was accurately estimated.

We investigated the low temperature formation of Pd2Si on Si(100) with TiN encapsulating layer formed at 500°C/1 min. Furthermore, the dopant segregation process was performed with ion dose of 1x1015 cm-2 for B+. The uniform Pd2Si was successfully formed with low sheet resistance of 10.4 Ω/sq. Meanwhile, the PtSi formed on Si(100) showed rough surface morphology if the silicidation temperature was 500°C. The estimated Schottky barrier height to hole of 0.20 eV (qφBp) was realized for n-Si(100).

This study tries to construct an accurate ranking method for five team ball games at the Olympic Games. First, the study uses a statistical rating method for team ball games. A single parameter, called a rating, shows the strength and skill of each team. We assume that the difference between the rating values explains the scoring ratio in a match based on a logistic regression model. The rating values are estimated from the scores of major international competitions that are held before the Rio Olympic Games. The predictions at the Rio Olympic Games demonstrate that the proposed method can more accurately predict the match results than the official world rankings or world ranking points. The proposed method enabled 262 correct predictions out of 370 matches, whereas using the official world rankings resulted in only 238 correct predictions. This result shows a significant difference between the two criteria.

Efficient road-lane detection is expected to be achievable by application of the Hough transform (HT) which realizes high-accuracy straight-line extraction from images. The main challenge for HT-hardware implementation in actual applications is the trade-off optimization between accuracy maximization, power-dissipation reduction and real-time requirements. We report a HT-hardware architecture for road-lane detection with parallelized voting procedure, local maximum algorithm and FPGA-prototype implementation. Parallelization of the global design is realized on the basis of θ-value discretization in the Hough space. Four major hardware modules are developed for edge detection in the original video frames, computation of the characteristic edge-pixel values (ρ,θ) in Hough-space, voting procedure for each (ρ,θ) pair with parallel local-maximum-based peak voting-point extraction in Hough space to determine the detected straight lines. Implementation of a prototype system for real-time road-lane detection on a low-cost DE1 platform with a Cyclone II FPGA device was verified to be possible. An average detection speed of 135 frames/s for VGA (640x480)-frames was achieved at 50 MHz working frequency.

This paper presents a rigorous analysis of the electromagnetic scattering and transmission of misaligned dual metallic grating screens. The Fourier transform and the mode-matching technique are employed to obtain an analytical solution. Numerical results show that misaligned dual metal grating screens exhibit asymmetric scattering and transmission properties with respect to the scattering and transmission angles. Parametric studies are conducted in terms of the lateral displacement and vertical distance between the dual metallic grating screens. For validation, the proposed method is compared with a numerical simulation and good agreement has been achieved.

In this paper, we consider a group testing (GT) problem. We derive a lower bound on the probability of error for successful decoding of defected binary signals. To this end, we exploit Fano's inequality theorem in the information theory. We show that the probability of error is bounded as an entropy function, a density of a pooling matrix and a sparsity of a binary signal. We evaluate that for decoding of highly sparse signals, the pooling matrix is required to be dense. Conversely, if dense signals are needed to decode, the sparse pooling matrix should be designed to achieve the small probability of error.

In content oriented networks (CON), routers in a network are generally equipped with local cache storages and store incoming contents temporarily. Efficient utilization of total cache storage in networks is one of the most important technical issues in CON, as it can reduce content server load, content download latency and network traffic. Performance of networked cache is reported to strongly depend on both cache decision and content request routing. In this paper, we evaluate several combinations of these two strategies. Especially for routing, we take up off-path cache routing, Breadcrumbs, as one of the content request routing proposals. Our performance evaluation results show that off-path cache routing, Breadcrumbs, suffers low performance with cache decisions which generally has high performance with shortest path routing (SPR), and obtains excellent performance with TERC (Transparent En-Route Cache) which is well-known to have low performance with widely used SPR. Our detailed evaluation results in two network environments, emerging CONs and conventional IP, show these insights hold in both of these two network environments.

The technology advancement of satellite instruments requires increasingly fast interconnection technologies, for which no standardised solution exists. SpaceFibre is the forthcoming protocol promising to overcome the limitation of its predecessor SpaceWire, offering data-rate higher than 1Gbps. However, while several implementations of the SpaceFibre IP already exist, its Network Layer is still at experimental level. This article describes the architecture of an implemented SpaceFibre Routing Switch and provides synthesis results for common FPGAs.

Since the hardware resource of a single FPGA is limited, one idea to scale the performance of FPGA-based HPC applications is to expand the design space with multiple FPGAs. This paper presents a scalable architecture of a deeply pipelined stream computing platform, where available parallelism and inter-FPGA link characteristics are investigated to achieve a scaled performance. For a practical exploration of this vast design space, a performance model is presented and verified with the evaluation of a tsunami simulation application implemented on Intel Arria 10 FPGAs. Finally, scalability analysis is performed, where speedup is achieved when increasing the computing pipeline over multiple FPGAs while maintaining the problem size of computation. Performance is scaled with multiple FPGAs; however, performance degradation occurs with insufficient available bandwidth and large pipeline overhead brought by inadequate data stream size. Tsunami simulation results show that the highest scaled performance for 8 cascaded Arria 10 FPGAs is achieved with a single pipeline of 5 stream processing elements (SPEs), which obtained a scaled performance of 2.5 TFlops and a parallel efficiency of 98%, indicating the strong scalability of the multi-FPGA stream computing platform.

This paper looks into the underlying RF energy harvesting issues at low input ambient power levels below 0 dBm where efficiency degradation is severe. The proposed design aims to improve the rectenna sensitivity, efficiency, and output DC power. In the same manner, we are using a straightforward and compact size rectenna design. The receiving antenna is a coplanar waveguide (CPW) slot monopole antenna with harmonic suppression property and a peak measured gain of 3 dBi. Also, an improved antenna radiation characteristics, e.g radiation pattern and gain covering the desired operating band (ISM 2.45 GHz), is observed. The rectifier is a voltage doubler circuit based on microstrip (MS) structure. Two architectures of rectenna were carefully designed, fabricated and tested. The first layout; antenna, and rectifier were fabricated separately and then connected using a connector. The peak efficiency (40% at -5 dBm) achieved is lower than expected. To improve the efficiency, a high compactness and simple integration between antenna and rectifier are achieved by using a smooth CPW-MS transition. This design shows improved conversion efficiency measurement results which typically agree with the simulation results. The measured peak conversion efficiency is 72% at RF power level of -7 dBm and a load resistance of 2 kΩ.

Accounting for the exponential increase in security threats, the development of new defense strategies for pervasive environments is acquiring an ever-growing importance. The expected avalanche of heterogeneous IoT devices which will populate our industrial factories and smart houses will increase the complexity of managing security requirements in a comprehensive way. To this aim, cloud-based security services are gaining notable impetus to provide security mechanisms according to Security-as-a-Service (SECaaS) model. However, the deployment of security applications in remote cloud data-centers can introduce several drawbacks in terms of traffic overhead and latency increase. To cope with this, Edge Computing can provide remarkable advantages avoiding long routing detours. On the other hand, the limited capabilities of edge node introduce potential constraints in the overall management. This paper focuses on the provisioning of virtualized security services in resource-constrained edge nodes by leveraging lightweight virtualization technologies. Our analysis aims at shedding light on the feasibility of container-based security solutions, thus providing useful guidelines towards the orchestration of security at the edge. Our experiments show that the overhead introduced by the containerization is very light.

Very few existing works about inertial sensor based air-writing focused on writing constraints' effects on recognition performance. We proposed a LSTM-based system and made several quantitative analyses under different constraints settings against CHMM, DTW-AP and CNN. The proposed system shows its advantages in accuracy, real-time performance and flexibility.

In this paper, a scramble phase assisting weighted-type fractional Fourier transform (SPA-WFRFT) based system is proposed to guarantee the communication's security. The original transmitting signal is divided into two parts. The first part is modulated by WFRFT and subsequently makes up the constellation beguiling. The other part is used to generate the scramble phase and also to assist in the encryption of the WFRFT modulated signal dynamically. The novel constellation optimal model is built and solved through the genetic algorithm (GA) for the constellation beguiling. And the double pseudo scheme is implemented for the scramble phase generation. Theoretical analyses show that excellent security performances and high spectral efficiency can be attained. Final simulations are carried out to evaluate the performances of the SPA-WFRFT based system, and demonstrate that the proposed system can effectively degrade the unauthorized receivers' bit error rate (BER) performance while maintaining its own communication quality.

Approximate computing is a promising paradigm to realize fast, small, and low power characteristics, which are essential for modern applications, such as Internet of Things (IoT) devices. This paper proposes the Carry-Predicting Adder (CPredA), an approximate adder that is scalable relative to accuracy and power consumption. The proposed CPredA improves the accuracy of a previously studied adder by performing carry prediction. Detailed simulations reveal that, compared to the existing approximate adder, accuracy is improved by approximately 50% with comparable energy efficiency. Two application-level evaluations demonstrate that the proposed approximate adder is sufficiently accurate for practical use.

Link-level and node-level blocking in photonic networks has been intensively investigated for several decades and the C/D/C approach to OXCs/ROADMs is often emphasized. However, this understanding will have to change in the future large traffic environment. We herein elucidate that exploiting node-level blocking can yield cost-effective large-capacity wavelength routing networks in the near future. We analyze the impact of link-level and node-level blocking in terms of traffic demand and assess the fiber utilization and the amount of hardware needed to develop OXCs/ROADMs, where the necessary number of link fibers and that of WSSs are used as metrics. We clarify that the careful introduction of node-level blocking is the more effective direction in creating future cost effective networks; compared to C/D/C OXCs/ROADMs, it offers a more than 70% reduction in the number of WSSs while the fiber increment is less than ~2%.

In this paper, we briefly review the concept of superconducting quantum computers and discuss their hardware architecture. We also describe the necessary technologies for the development of a medium-scale quantum computer with more than tens of thousands of quantum bits.

If a shared IP network is to deliver large-volume streaming media content, such as real-time videos, we need a technique for explicitly setting and dynamically changing the transmission paths used to respond to the congestion situation of the network, including multi-path transmission of a single-flow, to maximize network bandwidth utilization and stabilize transmission quality. However, current technologies cannot realize flexible multi-path transmission because they require complicated algorithms for route searching and the control load for route changing is excessive. This paper proposes a scheme that realizes routing control for multi-path transmission by combining multiple virtual networks on the same physical network. The proposed scheme lowers the control load incurred in creating a detour route because routing control is performed by combining existing routing planes. In addition, our scheme simplifies route searching procedure because congestion avoidance control of multi-path transmission can be realized by the control of a single path. An experiment on the JGN-X network virtualization platform finds that while the time taken to build an inter-slice link must be improved, the time required to inspect whether each slice has virtual nodes that can be connected to the original slice and be used as a detour destination can be as short as 40 microseconds per slice even with large slices having more than 100 virtual nodes.

Increasing hardware resources, such as multi-core and multi-socket CPUs, memory capacity and high-speed NICs, impose significant challenges on Network Function Virtualization (NFV) backends. They increase the potential numbers of per-server NFs or tenants, which requires a packet switching architecture that is not only scalable to large number of virtual ports, but also robust to attacks on the data plane. This is a real problem; a recent study has reported that Open vSwitch, a widely used software switch, had a buffer-overflow bug in its data plane that results the entire SDN domain to be hijacked by worms propagated in the network. In order to address this problem, we propose REdge. It scales to thousands of virtual ports or NFs (as opposed to hundreds in the current state-of-the art), and protect modular, flexible packet switching logic against various bugs, such as buffer overflow and other unexpected operations using static program checking. When 2048 NFs are active and packets are distributed to them based on the MAC or IP addresses, REdge achieves 3.16 Mpps or higher packet forwarding rates for 60 byte packets and achieves the wire rate for 1500 byte packets in the 25 Gbps link.