This paper derives highly accurate and effective closed-form formulas for the average upper bound on the pairwise error probability (PEP) of the multi-carrier index keying orthogonal frequency division multiplexing (MCIK-OFDM) system with low-complexity detection (i.e., greedy detection) in two-wave with diffuse power (TWDP) fading channels. To be specific, we utilize an exact moment generating function (MGF) of the signal-to-noise ratio (SNR) under TWDP fading to guarantee highly precise investigations of error probability performance; existing formulas for average PEP employ the approximate probability density function (PDF) of the SNR for TWDP fading, thereby inducing inherent approximation error. Moreover, some special cases of TWDP fading are also considered. To quantitatively reveal the achievable modulation gain and diversity order, we further derive asymptotic formulas for the upper bound on the average PEP. The obtained asymptotic expressions can be used to rapidly estimate the achievable error performance of MCIK-OFDM with the greedy detection over TWDP fading in high SNR regimes.

This paper proposes route advertisement policies (RAP) and an inbound traffic engineering (ITE) technique for a multihomed autonomous system (AS) employing the Border Gateway Protocol (BGP) and provider aggregatable (PA) addressing. The proposed RAP avail the advantage of address aggregation benefit of PA addressing. If multiple address spaces are allocated to each of the ASes that are multihomed to multiple upstream ASes, reduction of the forwarding information base (FIB) and quick convergence are achieved. However, multihoming based on PA addressing raises two issues. First, more specific address information is hidden due to address aggregation. Second, multiple allocated address spaces per AS does not provide the capability of ITE. To cope with these two limitations, we propose i) RAP to ensure connectivity among ASes with fewer routes installed in the FIB of each top-tier AS, and ii) an ITE technique to control inbound routes into multihomed ASes. Our ITE technique does not increase the RIB and FIB sizes in the Internet core. We implement the proposed RAP in an emulation environment with BGP using the Quagga software suite and our developed Hierarchical Automatic Number Allocation (HANA) protocols. We use HANA as a tool to automatically allocate hierarchical PA addresses to ASes. We confirm that with our proposed policies the FIB and RIB (routing information base) sizes in tier-1 ASes do not change with the increase of tier-3 ASes, and the number of BGP update messages exchanged is reduced by up to 69.9% from that achieved with conventional BGP RAP. We also confirmed that our proposed ITE technique, based on selective prefix advertisement, can indeed control inbound traffic into a multihomed AS employing PA addressing.

In this research, we propose an effective stability analysis method to impacting systems with periodically moving borders (periodic borders). First, we describe an n-dimensional impacting system with periodic borders. Subsequently, we present an algorithm based on a stability analysis method using the monodromy matrix for calculating stability of the waveform. This approach requires the state-transition matrix be related to the impact phenomenon, which is known as the saltation matrix. In an earlier study, the expression for the saltation matrix was derived assuming a static border (fixed border). In this research, we derive an expression for the saltation matrix for a periodic border. We confirm the performance of the proposed method, which is also applicable to systems with fixed borders, by applying it to an impacting system with a periodic border. Using this approach, we analyze the bifurcation of an impacting system with a periodic border by computing the evolution of the stable and unstable periodic waveform. We demonstrate a discontinuous change of the periodic points, which occurs when a periodic point collides with a border, in the one-parameter bifurcation diagram.

Formal series are a natural extension of formal languages by associating each word with a value called a coefficient or a weight. Among them, recognizable series and algebraic series can be regarded as extensions of regular languages and context-free languages, respectively. The coefficient of a word w can represent quantities such as the cost taken by an operation on w, the probability that w is emitted. One of the possible applications of formal series is the string counting in quantitative analysis of software. In this paper, we define the counting problems for formal series and propose algorithms for the problems. The membership problem for an automaton or a grammar corresponds to the problem of computing the coefficient of a given word in a given series. Accordingly, we define the counting problem for formal series in the following two ways. For a formal series S and a natural number d, we define CC(S,d) to be the sum of the coefficients of all the words of length d in S and SC(S,d) to be the number of words of length d that have non-zero coefficients in S. We show that for a given recognizable series S and a natural number d, CC(S,d) can be computed in O(η log d) time where η is an upper-bound of time needed for a single state-transition matrix operation, and if the state-transition matrices of S are commutative for multiplication, SC(S,d) can be computed in polynomial time of d. We extend the notions to tree series and discuss how to compute them efficiently. Also, we propose an algorithm that computes CC(S,d) in square time of d for an algebraic series S. We show the CPU time of the proposed algorithm for computing CC(S,d) for some context-free grammars as S, one of which represents the syntax of C language. To examine the applicability of the proposed algorithms to string counting for the vulnerability analysis, we also present results on string counting for Kaluza Benchmark.

We have previously introduced the static dependency pair method that proves termination by analyzing the static recursive structure of various extensions of term rewriting systems for handling higher-order functions. The key is to succeed with the formalization of recursive structures based on the notion of strong computability, which is introduced for the termination of typed λ-calculi. To bring the static dependency pair method close to existing functional programs, we also extend the method to term rewriting models in which functional abstractions with patterns are permitted. Since the static dependency pair method is not sound in general, we formulate a class; namely, accessibility, in which the method works well. The static dependency pair method is a very natural reasoning; therefore, our extension differs only slightly from previous results. On the other hand, a soundness proof is dramatically difficult.

The traditional tests are planned and designed at the early stages, but it is possible to execute test cases after implementing source code. Since there is a time difference between design stage and testing stage, by the time a software design error is found it will be too late. To solve this problem, this paper suggests a virtual pre-testing process. While the virtual pre-testing process can find software and testing errors before the developing stage, it can automatically generate and execute test cases with modeling and simulation (M&S) in a virtual environment. The first part of this method is to create test cases with state transition tree based on state diagram, which include state, transition, instruction pair, and all path coverage. The second part is to model and simulate a virtual target, which then pre-test the target with test cases. In other words, these generated test cases are automatically transformed into the event list. This simultaneously executes test cases to the simulated target within a virtual environment. As a result, it is possible to find the design and test error at the early stages of the development cycle and in turn can reduce development time and cost as much as possible.

Automatic speech recognition (ASR) and keyword search (KWS) have more and more found their way into our everyday lives, and their successes could boil down lots of factors. In these factors, large scale of speech data used for acoustic modeling is the key factor. However, it is difficult and time-consuming to acquire large scale of transcribed speech data for some languages, especially for low-resource languages. Thus, at low-resource condition, it becomes important with which transcribed data for acoustic modeling for improving the performance of ASR and KWS. In view of using acoustic data for acoustic modeling, there are two different ways. One is using the target language data, and another is using large scale of other source languages data for cross-lingual transfer. In this paper, we propose some approaches for efficient selecting acoustic data for acoustic modeling. For target language data, a submodular based unsupervised data selection approach is proposed. The submodular based unsupervised data selection could select more informative and representative utterances for manual transcription for acoustic modeling. For other source languages data, the high misclassified as target language based submodular multilingual data selection approach and knowledge based group multilingual data selection approach are proposed. When using selected multilingual data for multilingual deep neural network training for cross-lingual transfer, it could improve the performance of ASR and KWS of target language. When comparing our proposed multilingual data selection approach with language identification based multilingual data selection approach, our proposed approach also obtains better effect. In this paper, we also analyze and compare the language factor and the acoustic factor influence on the performance of ASR and KWS. The influence of different scale of target language data on the performance of ASR and KWS at mono-lingual condition and cross-lingual condition are also compared and analyzed, and some significant conclusions can be concluded.

A novel adaptive code division multiplexing system with hybrid electrical and optical codes is proposed for flexible and dynamic resource allocation in next generation asynchronous optical access networks. We analyze the performance of a 10Gbps × 12 optical node unit, using hierarchical 8-level optical and 4-level electrical phase shift keying codes.

Nuclear power plants require in-vessel inspections for soundness checks and preventive maintenance. One inspection procedure is visual testing (VT), which is based on video images of an underwater camera in a nuclear reactor. However, a lot of noise is superimposed on VT images due to radiation exposure. We propose a technique for improving the quality of those images by image processing that reduces radiation noise and enhances signals. Real-time video processing was achieved by applying the proposed technique with a parallel processing unit. Improving the clarity of VT images will lead to reducing the burden on inspectors.

In social networks, predicting user behavior under social hotspots can aid in understanding the development trend of a topic. In this paper, we propose a retweeting prediction method for social hotspots based on tensor decomposition, using user information, relationship and behavioral data. The method can be used to predict the behavior of users and analyze the evolvement of topics. Firstly, we propose a tensor-based mechanism for mining user interaction, and then we propose that the tensor be used to solve the problem of inaccuracy that arises when interactively calculating intensity for sparse user interaction data. At the same time, we can analyze the influence of the following relationship on the interaction between users based on characteristics of the tensor in data space conversion and projection. Secondly, time decay function is introduced for the tensor to quantify further the evolution of user behavior in current social hotspots. That function can be fit to the behavior of a user dynamically, and can also solve the problem of interaction between users with time decay. Finally, we invoke time slices and discretization of the topic life cycle and construct a user retweeting prediction model based on logistic regression. In this way, we can both explore the temporal characteristics of user behavior in social hotspots and also solve the problem of uneven interaction behavior between users. Experiments show that the proposed method can improve the accuracy of user behavior prediction effectively and aid in understanding the development trend of a topic.

The physics and applications of superconducting phase shifts and their control in superconducting systems are reviewed herein. The operation principle of almost all superconducting devices is related to the superconducting phase, and an efficient control of the phase is crucial for improving the performance and scalability. Furthermore, employing new methods to shift or control the phase may lead to the development of novel superconducting device applications, such as cryogenic memory and quantum computing devices. Recently, as a result of the progress in nanofabrication techniques, superconducting phase shifts utilizing π states have been realized. In this review, following a discussion of the basic physics of phase propagation and shifts in hybrid superconducting structures, interesting phenomena and device applications in phase-shifted superconducting systems are presented. In addition, various possibilities for developing electrically and magnetically controllable 0 and π junctions are presented; these possibilities are expected to be useful for future devices.

We have been investigating reversible quantum-flux-parametron (RQFP), which is a reversible logic gate using adiabatic quantum-flux-parametron (AQFP), toward realizing superconductor reversible computing. In this paper, we review the recent progress of RQFP. Followed by a brief explanation on AQFP, we first review the difference between irreversible logic gates and RQFP in light of time evolution and energy dissipation, based on our previous studies. Numerical calculation results reveal that the logic state of RQFP can be changed quasi-statically and adiabatically, or thermodynamically reversibly, and that the energy dissipation required for RQFP to perform a logic operation can be arbitrarily reduced. Lastly, we show recent experimental results of an RQFP cell, which was newly designed for the latest cell library. We observed the wide operation margins of more than 4.7dB with respect to excitation currents.

We report the characterization of hysteresis in SOI-based super-steep subthreshold slope FETs, which are conventional floating body and body-tied, and newly proposed PN-body-tied structures. We found that the hysteresis widths of the PN-body-tied structures are smaller than that of the conventional floating body and body-tied structures; this means that they are feasible for switching devices. Detailed characterizations of the hysteresis widths of each device are also reported in the study, such as dependency on the gate length and the impurity concentration.

We present a concept of an advanced rapid single-flux-quantum (RSFQ) logic circuit family using the combination of 0-shifted and π-shifted Josephson junctions. A π-shift in the current-phase relationship can be obtained in several types of Josephson junctions, such as Josephson junctions containing a ferromagnet barrier layer, depending on its thickness and temperature. We use a superconducting quantum interference devices composed of a pair of 0- and π-shifted Josephson junctions (0-π SQUIDs) as a basic circuit element. Unlike the conventional RSFQ logic, bistability is obtained by spontaneous circular currents without using a large superconductor loop, and the state can be flipped by smaller driving currents. These features lead to energy- and/or space-efficient logic gates. In this paper, we show several example circuits where we represent signals by flips of the states of a 0-π SQUID. We obtained successful operation of the circuits from numerical simulation.

This paper presents a self-calibrating dynamic latched comparator with a stochastic offset voltage detector that can be realized by using simple digital circuitry. An offset voltage of the comparator is compensated by using a statistical calibration scheme, and the offset voltage detector uses the uncertainty in the comparator output. Thanks to the simple offset detection technique, all the calibration circuitry can be synthesized using only standard logic cells. This paper also gives a design methodology that can provide the optimal design parameters for the detector on the basis of fundamental statistics, and the correctness of the design methodology was statistically validated through measurement. The proposed self-calibrating comparator system was fabricated in a 180 nm 1P6M CMOS process. The prototype achieved a 38 times improvement in the three-sigma of the offset voltage from 6.01 mV to 158 µV.

We have studied on thermally assisted nano-structured transistors made of superconductor ultra-thin films. These transistors potentially work as interface devices for Josephson-CMOS (complementary metal oxide semiconductor) hybrid memory systems, because they can generate a high output voltage of sub-V enough to drive a CMOS transistor. In addition, our superconductor transistors are formed with very fine lines down to several tens of nm in widths, leading to very small foot print enabling us to make large capacity hybrid memories. Our superconductor transistors are made with niobium titanium nitride (NbTiN) thin films deposited on thermally-oxidized silicon substrates, on which other superconductor circuits or semiconductor circuits can be formed. The NbTiN thickness dependence of the critical temperature and of resistivity suggest thermally activated vortex or anti-vortex behavior in pseudo-two-dimensional superconducting films plays an important role for the operating principle of the transistors. To show the potential that the transistors can drive MOS transistors, we analyzed the driving ability of the superconductor transistors with HSPICE simulation. We also showed the turn-on behavior of a MOS transistor used for readout of a CMOS memory cell experimentally. These results showed the high potential of superconductor transistors for Josephson-CMOS hybrid memories.

We describe the design and simulation of a suitable branching ratio for an optical coupler for a cable re-routing operation support system with no service interruption, and report our experimental results. We also show the risk analysis, and report that the branching ratio was 0.47 where the probability was 99.7% that the maximum acceptable cable loss of a detour line was more than that of the current line.

3D ball tracking is of great significance in ping-pong game analysis, which can be utilized to applications such as TV contents and tactic analysis, with some of them requiring real-time implementation. This paper proposes a CPU-GPU platform based Particle Filter for multi-view ball tracking including 4 proposals. The multi-peak estimation and the ball-like observation model are proposed in the algorithm design. The multi-peak estimation aims at obtaining a precise ball position in case the particles' likelihood distribution has multiple peaks under complex circumstances. The ball-like observation model with 4 different likelihood evaluation, utilizes the ball's unique features to evaluate the particle's similarity with the target. In the GPU implementation, the double-queue structure and the vectorized data combination are proposed. The double-queue structure aims at achieving task parallelism between some data-independent tasks. The vectorized data combination reduces the time cost in memory access by combining 3 different image data to 1 vector data. Experiments are based on ping-pong videos recorded in an official match taken by 4 cameras located in 4 corners of the court. The tracking success rate reaches 99.59% on CPU. With the GPU acceleration, the time consumption is 8.8 ms/frame, which is sped up by a factor of 98 compared with its CPU version.

The elastic optical network (EON) is a promising new optical technology that uses spectrum resources much more efficiently than does traditional wavelength division multiplexing (WDM). This paper focuses on the routing, modulation level, spectrum and transceiver allocation (RMSTA) problems of the EON. In contrast to previous works that consider only the routing and spectrum allocation (RSA) or routing, modulation level and spectrum allocation (RMSA) problems, we additionally consider the transceiver allocation problem. Because transceivers can be used to regenerate signals (by connecting two transceivers back-to-back) along a transmission path, different regeneration sites on a transmission path result in different spectrum and transceiver usage. Thus, the RMSTA problem is both more complex and more challenging than are the RSA and RMSA problems. To address this problem, we first propose an integer linear programming (ILP) model whose objective is to optimize the balance between spectrum usage and transceiver usage by tuning a weighting coefficient to minimize the cost of network operations. Then, we propose a novel virtual network-based heuristic algorithm to solve the problem and present the results of experiments on representative network topologies. The results verify that, compared to previous works, the proposed algorithm can significantly reduce both resource consumption and time complexity.

CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.