Object tracking is a major technique in image processing and computer vision. Tracking speed will directly determine the quality of applications. This paper presents a parallel implementation for a recently proposed scale- and rotation-invariant on-line object tracking system. The algorithm is based on NVIDIA's Graphics Processing Units (GPU) using Compute Unified Device Architecture (CUDA), following the model of single instruction multiple threads. Specifically, we analyze the original algorithm and propose the GPU-based parallel design. Emphasis is placed on exploiting the data parallelism and memory usage. In addition, we apply optimization technique to maximize the utilization of NVIDIA's GPU and reduce the data transfer time. Experimental results show that our GPGPU-based method running on a GTX480 graphics card could achieve up to 12X speed-up compared with the efficiency equivalence on an Intel E8400 3.0 GHz CPU, including I/O time.

Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.

In recent Printed Circuit Boards (PCB), the design size and density have increased, and the improvement of routing tools for PCB is required. There are several routing tools which generate high quality routing patterns when connection requirement can be realized by horizontal and vertical segments only. However, in high density PCB, the connection requirements cannot be realized when only horizontal and vertical segments are used. Up to one third nets can not be realized if no non-orthogonal segments are used. In this paper, a routing method for a single-layer routing area that handles higher density designs in which 45-degree segments are used locally to relax the routing density is introduced. In the proposed method, critical zones in which non-orthogonal segments are required in order to realize the connection requirements are extracted, and 45-degree segments are used only in these zones. By extracting minimal critical zones, the other area that can be used to improve the quality of routing pattern without worry about connectivity issues is maximized. Our proposed method can utilize the routing methods which generate high quality routing pattern even if they only handle horizontal and vertical segments as subroutines. Experiments show that the proposed method analyzes a routing problem properly, and that the routing is realized by using 45-degree segments effectively.

BGP dictates routing between autonomous systems with rich policy mechanisms in today's Internet. Operators translate high-level policy principles into low-level configurations of multiple routers without a comprehensive understanding of the actual effect on the network behaviors, making the routing management and operation an error-prone and time-consuming procedure. A fundamental question to answer is: how to verify the intended routing principles against the actual routing effects of an ISP? In this paper, we develop a methodology RPIM (Routing Policy Inference Model) towards this end. RPIM extracts from the routing tables various policy patterns, which represent certain high-level policy intentions of network operators, and then maps the patterns into specific design primitives that the ISP employs. To the best of our knowledge, we are the first to infer routing policies in ISP networks comprehensively from the aspects of business relationship, traffic engineering, scalability and security. We apply RPIM to 11 ASes selected from RIPE NCC RIS project, and query IRR database to validate our approach. Vast majority of inferred policies are confirmed by the policy registries, and RPIM achieves 96.23% accuracy excluding validation difficulties caused by incompleteness of the IRR database.

Recently, the need for multimedia devices, such as mobile phones, digital TV, PMP, digital camcorders, digital cameras has increased. These devices provide various services for multimedia file manipulation, allowing multimedia contents playback, multimedia file editing, etc. Additionally, digital TV provides a recorded multimedia file copy to a portable USB disk. However, Linux Ext3 file system, as employed by these devices, has a lot of drawbacks, as it required a considerable amount of time and disk I/Os to store large-size edited multimedia files, and it is hard to access for typical PC users. Therefore, in this paper a design and implementation of an amortized Ext3 with FWAE (Fast Writing-After-Editing) for WinXP-based multimedia applications is described. The FWAE is a fast and efficient multimedia file editing/storing technique for the Ext3 that exploits inode block pointer re-setting and shared data blocks by simply modifying metadata information. Individual experiments in this research show that the amortized Ext3 with FWAE for WinXP not only dramatically improves written performance of the Ext3 by 16 times on average with various types of edited multimedia files but also notably reduces the amount of consumed disk space through data block sharing. Also, it provides ease and comfort to use for typical PC users unfamiliar with Linux OS.

The many-to-one communication nature of wireless sensor networks (WSNs) leads to an unbalanced traffic distribution, and, accordingly, sensor nodes closer to the base station have to transmit more packets than those at the periphery of the network. This problem causes the nodes closer to the base station to deplete their energy prematurely, forming a hole surrounding the base station. This phenomenon is called the energy hole problem, and it severely reduces the network lifetime. In this paper, we present a cooperative power-aware routing algorithm for uniformly deployed WSNs. The proposed algorithm is based on the idea of replacing the constant transmission range of relaying sensor nodes with an adjusted transmission range, in such a way that each individual node consumes its energy smoothly. We formulate the dynamic transmission range adjustment optimization (DTA) problem as a 0-1 Multiple Choice Knapsack Problem (0-1 MCKP) and present a dynamic programming method to solve the optimization problem. Simulations confirm that the proposed method helps to balance the energy consumption of sensor nodes, avoiding the energy hole problem and extending the network lifetime.

Impulsive noise interference is a significant problem for the Integrated Services Digital Broadcasting for Terrestrial (ISDB-T) receivers due to its effect on the orthogonal frequency division multiplexing (OFDM) signal. In this paper, an adaptive scheme to suppress the effect of impulsive noise is proposed. The impact of impulsive noise can be detected by using the guard band in the frequency domain; furthermore the position information of the impulsive noise, including burst duration, instantaneous power and arrived time, can be estimated as well. Then a time-domain window function with adaptive parameters, which are decided in terms of the estimated information of the impulsive noise and the carrier-to-noise ratio (CNR), is employed to suppress the impulsive interference. Simulation results confirm the validity of the proposed scheme, which improved the bit error rate (BER) performance for the ISDB-T receivers in both AWGN channel and Rayleigh fading channel.

A novel grouping approach to segment text lines from handwritten documents is presented. In this text line segmentation algorithm, for each text line, a text string that connects the center points of the characters in this text line is built. The text lines are then segmented using the resulting text strings. Since the characters of the same text line are situated close together and aligned on a smooth curve, 2D tensor voting is used to reduce the conflicts when building these text strings. First, the text lines are represented by separate connected components. The center points of these connected components are then encoded by second order tensors. Finally, a voting process is applied to extract the curve saliency values and normal vectors, which are used to remove outliers and build the text strings. The experimental results obtained from the test dataset of the ICDAR 2009 Handwriting Segmentation Contest show that the proposed method generates high detection rate and recognition accuracy.

A 6–10-GHz broadband low noise amplifier (LNA) and transmitting amplifier (TA) for direct sequence ultra-wideband (DS-UWB) are presented. The LNA and TA are fabricated with the 0.18-µm 1P6M standard CMOS process. The CMOS LNA and TA are checked by on-wafer measurement with the DC supply voltage of 1.5 V. From 6–10 GHz, the broadband LNA exhibits a noise figure of 5.3–6.2 dB, a gain of 11–13.8 dB, a P1 dB of -15.7 - -10.8 dBm, a IIP3 of -5.5 - -1 dBm, a DC power consumption of 12 mW, and an input/output return loss higher than 11/12 dB, respectively. From 6–10 GHz, the broadband TA exhibits a gain of 7.6–10.5 dB, a OP1 dB of 2.8–6.1 dBm, a OIP3 of 12.3–15.1 dBm, and a PAE of 8.8–17.6% @ OP1 dB, and a η of 9.7–21.1% @ OP1 dB, and an input/output return loss higher than 6.8/3.2 dB, respectively.

Many scientific applications require efficient variable-precision floating-point arithmetic. This paper presents a special-purpose Very Large Instruction Word (VLIW) architecture for variable precision floating-point arithmetic (VV-Processor) on FPGA. The proposed processor uses a unified hardware structure, equipped with multiple custom variable-precision arithmetic units, to implement various variable-precision algebraic and transcendental functions. The performance is improved through the explicitly parallel technology of VLIW instruction and by dynamically varying the precision of intermediate computation. We take division and exponential function as examples to illustrate the design of variable-precision elementary algorithms in VV-Processor. Finally, we create a prototype of VV-Processor unit on a Xilinx XC6VLX760-2FF1760 FPGA chip. The experimental results show that one VV-Processor unit, running at 253 MHz, outperforms the approach of a software-based library running on an Intel Core i3 530 CPU at 2.93 GHz by a factor of 5X-37X for basic variable-precision arithmetic operations and elementary functions.

In MANET (Mobile Ad-hoc NETworks), there are two kinds of routing methods: proactive and reactive. Each has different characteristics and advantages. The latter generally employs the flooding technique to finding a routing path to the destination. However, flooding has big overheads caused by broadcasting RREQ packets to the entire network. Therefore, reducing this overhead is really needed to enable several network efficiencies. Previous studies introduced many approaches which are mainly concerned with the restriction of flooding. However, they usually configure the detailed routing path in the forward flooding procedure and ignore the factors causing the flooding overheads. In this paper, we propose the FSRS (First Search and Reverse Setting) routing protocol which is a new approach in flooding techniques and a new paradigm shift. FSRS is based on cluster topology and is composed of two main mechanisms: inter-cluster and intra-cluster flooding. Inter-cluster routing floods RREQ packets between cluster units and sets a cluster path. When the destination node receives the RREQ packet, it floods RREP packets to an intra-cluster destination which is a gateway to relay the RREP packet to a previous cluster. This is called intra-cluster routing. So to speak, a specific routing path configuration progresses in the RREP process through the reverse cluster path. Consequently, FSRS is a new kind of hybrid protocol well adapted to wireless ad-hoc networks. This suggests a basic wireless networking architecture to make a dynamic cluster topology in future work. In the simulation using NS-2, we compare it to several other protocols and verify that FSRS is a powerful protocol. In the result of the simulation, FSRS conserves energy by a maximum of 12% compared to HCR.

In cloud computing, a cloud user pays proportionally to the amount of the consumed resources (bandwidth, memory, and CPU cycles etc.). We posit that such a cloud computing system is vulnerable to DDoS (Distributed Denial-of-Service) attacks against quota. Attackers can force a cloud user to pay more and more money by exhausting its quota without crippling its execution system or congesting links. In this paper, we address this issue and claim that cloud should enable users to pay only for their admitted traffic. We design and prototype such a charging model in a CoreLab testbed infrastructure and show an example application.

Pedestrian detection from visual images, which is used for driver assistance or video surveillance, is a recent challenging problem. Co-occurrence histograms of oriented gradients (CoHOG) is a powerful feature descriptor for pedestrian detection and achieves the highest detection accuracy. However, its calculation cost is too large to calculate it in real-time on state-of-the-art processors. In this paper, to obtain optimal parallel implementation for an NVIDIA GPU, several kinds of parallelism of CoHOG-based detection are shown and evaluated suitability for implementation. The experimental result shows that the detection process can be performed at 16.5 fps in QVGA images on NVIDIA Tesla C1060 by optimized parallel implementation. By our evaluation, it is shown that the optimal strategy of parallel implementation for an NVIDIA GPU is different from that of FPGA. We discuss about the reason and show the advantages of each device. To show the scalability and portability of GPU implementation, the same object code is executed on other NVIDA GPUs. The experimental result shows that GTX570 can perform the CoHOG-based pedestiran detection 21.3 fps in QVGA images.

In this paper, we propose a two dimensional (2D) non-separable adaptive directional lifting (ADL) structure for discrete wavelet transform (DWT) and its image coding application. Although a 2D non-separable lifting structure of 9/7 DWT has been proposed by interchanging some lifting, we generalize a polyphase representation of 2D non-separable lifting structure of DWT. Furthermore, by introducing the adaptive directional filteringingto the generalized structure, the 2D non-separable ADL structure is realized and applied into image coding. Our proposed method is simpler than the 1D ADL, and can select the different transforming direction with 1D ADL. Through the simulations, the proposed method is shown to be efficient for the lossy and lossless image coding performance.

To reduce power consumption of wireless terminals, we have developed ultra-low leakage regulator circuits that control the intermittent terminal operation with very small activity ratio. The regulator circuits supply about 100 mA in the active mode and cut the leakage current to a nanoampere level in the standby mode. The operation of the ultralow-leakage regulator circuits with CMOS/SOI and bulk technologies is described. The leakage-current reduction mechanism in a proposed power switch with bulk technology is explained. Measurement shows that the power switch using reversely biased bulk transistors has a leakage current that is almost as small as that of conventional CMOS/SOI transistor switches.

This paper discusses recent developments for pattern recognition focusing on boosting approach in machine learning. The statistical properties such as Bayes risk consistency for several loss functions are discussed in a probabilistic framework. There are a number of loss functions proposed for different purposes and targets. A unified derivation is given by a generator function U which naturally defines entropy, divergence and loss function. The class of U-loss functions associates with the boosting learning algorithms for the loss minimization, which includes AdaBoost and LogitBoost as a twin generated from Kullback-Leibler divergence, and the (partial) area under the ROC curve. We expand boosting to unsupervised learning, typically density estimation employing U-loss function. Finally, a future perspective in machine learning is discussed.

This letter has retrained an MQDF classifier on the retraining set, which is constructed by samples locating near classification boundary. The method is evaluated on HCL2000 and HCD Chinese handwriting sets. The results show that the retrained MQDF outperforms MQDF and cascade MQDF on all test sets.

Previous studies of pattern recognition have shown that classifiers ensemble approaches can lead to better recognition results. In this paper, we apply the voting technique for the CoNLL-2010 shared task on detecting hedge cues and their scope in biomedical texts. Six machine learning-based systems are combined through three different voting schemes. We demonstrate the effectiveness of classifiers ensemble approaches and compare the performance of three different voting schemes for hedge cue and their scope detection. Experiments on the CoNLL-2010 evaluation data show that our best system achieves an F-score of 87.49% on hedge detection task and 60.87% on scope finding task respectively, which are significantly better than those of the previous systems.

A low-power low-noise intermediate-frequency (IF) circuit is proposed for Gaussian frequency shift keying (GFSK) low-IF receivers. The proposed IF circuit is realized by an all-analog architecture composed of a couple of limiting amplifiers (LAs) and received signal strength indicators (RSSIs), a couple of band-pass filters (BPFs), a frequency detector (FD), a low-pass filter (LPF) and a slicer. The LA and RSSI are realized by an optimized combination of folded amplifiers and current subtractor based rectifiers to avoid the process induced depressing on accuracy. In addition, taking into account the nonlinearity and static current of rectifiers, we propose an analytical model as an accurate approximation of RSSIs' transfer character. An active-RC based GFSK demodulation scheme is proposed, and then both low power consumption and a large dynamic range are obtained. The chip is implemented with HJTC 0.18 µm CMOS technology and measured under an intermediate frequency of 200 kHz, a data rate of 100 kb/s and a modulation index of 1. The RSSI has a dynamic range of 51 dB with a logarithmic linearity error of less than 1 dB, and the slope is 23.9 mV/dB. For 0.1% bit error ratio (BER), the proposed IF circuit has the minimum input signal-to-noise ratio (SNR) of 5 dB and an input dynamic range of 55.4 dB, whereas it can tolerate a frequency offset of -3%+9.5% at 6 dB input SNR. The total power consumption is 5.655.89 mW.

We review recently obtained results for CMOS (Complementary Metal Oxide Semiconductor) imaging devices used in biomedical applications. The topics include dish type image sensors, deep-brain implantation devices for small animals, and retinal prosthesis devices. Fundamental device structures and their characteristics are described, and the results of in vivo experiments are presented.