This paper proposes and investigates an intelligent error-controlling scheme according to different importance of segmental information. In particular, the scheme is designed for facial images encoded by model-based coding that is a kind of intelligent compression coding. Intelligent communication systems regard the contents of information to be transmitted with extremely high compression and reliability. After highly efficient information compression by model-beaed coding, errors in the compressed information lead to severe semantic errors. The proposed scheme reduces semantic errors of information for the receiver. In this paper, we consider Action Unit (AU) as a segment of model-based coded facial image of human being and define the importance for each AU. According to the importance, an AU is encoded by an appropriated code among codes with different error-correcting capabilities. For encoding with different error controlling codes, we use three kinds of constructions to obtain unequal error protection (UEP) codes in this paper. One of them is the direct sum construction and the others are the proposed constructions which are based on joint and double coding. These UEP codes can have higher coderate than other UEP codes when minimum Hamming distance is small. By using these UEP codes, the proposed intelligent error-controlling scheme can protect information in segment in order to reduce semantic errors over a conventional error-controlling scheme in which information is uniformly protected by an error-correcting code.

We present an 8-dimensional trellis-coded 8-PSK with a symbol transition constraint that is similar to that of π/4-shift quadrature phase shift keying (QPSK). This scheme can achieve a coding gain of 1.6 to 2.4 dB at the same rate of π/4-shift QPSK on Gaussian channel, and it has also an immunity against the integer multiples of 90 phase ambiguities. In order to label the constellation of the proposed scheme, a constellation partitioning algorithm is presented. This algorithm, on the basis of set partitioning, can be used to label the signal constellation with no coset structure.

Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

This papter proposes a new type of unidirectional error control codes which indicates the location of unidirectional errors clustered in b-bit length, i.e., unidirectional byte error in b (b2) bits. Single unidirectional b-bit byte error locating codes, called SUbEL codes, are first clarified using necessary and sufficient conditions, and then code construction algorithm is demonstrated. The lower bound on check bit length of the SUbEL codes is derived. Based on this, the proposed codes are shown to be very efficient. Using the code design concept presented for the SUbEL codes, it is demonstrated that generalized unidirectional byte error locating codes are easily constructed.

Recently, a lot of research works have been carried out regarding intelligent communication. If the final information sink is assumed as a human being, a communication channel can be used more effectively when encoders/decoders work "intelligently" or take into account of the semantics of information to be sent. We have been studying error-controlling systems based on different importance of segmental information. The system divides the information input into segments to which individual importance can be assigned. The segments are individually encoded by appropriate error-correcting codes (ECCs) which correspond to their importance among codes with different error-correcting capabilities. For the information that difference of the importance is systematically aligned, conventional UEP (unequal error protection) codes can be applied, but we treat the case that alignment of the importance of the information source is not systematically aligned. Since the system uses multiple ECCs with different (n,k,d) parameters, information regarding what length of the next codeword is required for decoding. We propose error controlling schemes using mulriple ECCs; the first scheme and the second scheme use the obvious codelength identifying information. In the second scheme, information bits are sorted so that segments with the same importance can be encoded by an ECC with the same error-correcting capability. The third scheme is a main proposal in this paper and uses Variable Capability Coding scheme (VCC) which uses some ECCs having different error-correcting capabilities and codelengths. A sequence encoded by the VCC is separable into appropriate segments without obvious codelength identifying information when the channel error probability is low. Subsequently, we evaluate these schemes by coderate when (1) error correcting capability (2) codelength identifying capability are the same. One of the feature of VCC is the capability of resuming from propagative errors because errors beyond the codelength identifying capability occur and the proper beginning of the codeword is lost in the decoder. We also evaluate this capability as (3) resynchronizing capability.

This paper describes highly parallel analog image coding and decoding by cellular neural networks (CNNs). The communication system in which the coder (C-) and decoder (D-) CNNs are embedded consists of a differential transmitter with an internal receiver model in the feedback loop. The C-CNN encodes the image through two cascaded techniques: structural compression and halftoning. The D-CNN decodes the received data through a reconstruction process, which includes a dynamic current distribution, so that the original input to the C-CNN can be recognized. The halftoning serves as a dynamic quantization to convert each pixel to a binary value depending on the neighboring values. We approach halftoning by the minimization of error energy between the original gray image and reconstructed halftone image, and the structural compression from the viewpoints of topological and regularization theories. All dynamics are described by CNN state equations. Both the proposed coding and decoding algorithms use only local image information in a space inveriant manner, therefore errors are distributed evenly and will not introduce the blocking effects found in DCT-based coding methods. In the future, the use of parallel inputs from on-chip photodetectors would allow direct dynamic quantization and compression of image sequences without the use of multiple bit analog-to-digital converters. To validate our theory, a simulation has been performed by using the relaxation method on an 150 frame image sequence. Each input image was 256256 pixels whth 8 bits per pixel. The simulated fixed compression rate, not including the Huffman coding, was about 1/16 with a PSNR of 31[dB]35[dB].

In the actual acoustic environment, the stochastic process exhibits various non-Gaussian distribution forms, and there exist potentially various nonlinear correlations in addition to the linear correlation between time series. In this study, a nonlinear ARMA model is proposed, based on the Bayes' theorem, where no artificially pre-established regression function model is assumed between time series, while reflecting hierarchically all of those various correlation informations. The proposed method is applied to the actual data of road traffic noise and its practical usefulness is verified.

This paper describes a pipelining universal system of discrete time cellular neural networks (DTCNNs). The new relaxation-based algorithm which is called a Pipelining Gauss Seidel (PGS) method is used to solve the CNN state equations in pipelining. In the systolic system of N processor elements {PEi}, each PEi performs the convolusional computation (CC) of all cells and the preceding PEi-1 performs the CC of all cells taking precedence over it by the precedence interval number p. The expected maximum number of PE's for the speeding up is given by n/p where n means the number of cells. For its application, the encoding and decoding process of moving images is simulated.

A new recursive method for obtaining the mean waiting time in a polling system with general service order and gated service discipline is proposed. The analytical approach used to obtain the mean waiting time is via an imbedded Markov chain and a new recursive method is used to obtain the moments of pseudocycle time which are parameters in the formula for the mean waiting time. This method is computationally tractable, so the analytical results can cover a wide range of applications. Simulations are also conducted to verify the validity of the analysis.

This paper proposes a new burst coherent demodulator that improves transmission quality of microcellular TDMA/TDD systems for personal communications and has configuration suitable for low power consumption with LSIC-implementation. To achieve the better transmission quality, the proposed demodulator employs coherent detection with a unique carrier recovery scheme that can operate without any preamble for carrier recovery. In addition, the demodulator uses a clock recovery scheme with clock phase estimation using twice differentiation, which eliminates hangup and attains fast clock acquisition at 2 samples/symbol. Experimental results clarify the superiority of the proposed coherent demodulator for microcellular TDMA/TDD systems. The proposed coherent demodulator reduces the irreducible frame error rate by 40%, and achieves 4dB improvement at the frame error rate of 10% compared with differential detection under the Rayleigh fading (fD/fs=810-5, τrms/Ts=510-2) typical of personal communication environments.

The demand for mobile communication services is rapidly increasing, because the mobile communication service is synonymy of an ideal communication style realizing communication in anytime, anywhere and with anyone. The development of economic and social activities is a primary factor of the increasing demand for mobile communication services. The demand stimulates the development of technology in mobile communication including personal communication services. Thus mobile communication has been one of the most active research in communications in the last several years. There exist various problems to which graph & network theory is applicable in mobile communication services (for example, channel assignment algorithm in cellular system, protocol in modile communication networks and traffic control in mobile communication ). A model of a cellular system has been formulated using a graph and it is known that the channel assignment problem is equivalent to the coloring problem of graph theory. Recently, two types of coloring problems on graphs or networks related to the channel assignment problem were proposed. Mainly, we introduce these coloring problems and show some results on these problems in this paper.

This paper gives field experimental results on 16-ary quadrature amplitude modulation/time division multiple access (16QAM/TDMA) and trellis coded 16QAM/TDMA systems for land mobile communications in order to evaluate its capability of achieving large capacity and high quality data transmission. Pilot symbol aided space diversity and symbol timing synchronization based on maximum likelihood (ML) estimation are applied to both 16QAM/TDMA and trellis coded 16QAM/TDMA to improve transmission quality. For the trellis coded 16QAM/TDMA, trellis coding with Viterbi decoding and 2-frame symbol interleaving are further employed. The field experiments were conducted in the Tokyo metropolitan area of Japan. The results show that 16QAM/TDMA and trellis coded 16QAM/TDMA are practical modulation/access schemes for land mobile communication systems.

This paper presents a new line extraction method to capture vectors based on contours and skeletons from line drawing raster images in which the lines are touched by characters or other lines. Conventionally, two line extraction methods have generally been used. One is a thinning method. The other is a medial line extraction method based on parallel pairs of contours. The thinning method tends to distort the extracted lines, especially at intersections and corners. On the other hand, the medial line extraction method has a poor capability as regards capturing correct lines at intersections. Contours are able to maintain edge shapes well, while skeletons preserve topological features; thus, a combination of these features effectively leads to the best fitting line. In the proposed method, the line which best fits the original image is selected from among various candidate lines. The candidates are created from several merged short skeleton fragments located between pairs of short contour fragments. The method is also extended to circular arc fitting. Experimental results show that the proposed line fitting method is effective.

This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

This paper presents an overview of the SDC-I (Super Database Computer I) developed at the University of Tokyo, Japan. The purpose of the project was to build a high performance SQL server which emphasizes query processing over transaction processing. Recently relational database systems tend to be used for heavy decision support queries, which include many join, aggregation, and order-by operations. At present high-end mainframes are used for these applications requiring several hours in some cases. While the system architecture for high traffic transaction processing systems is well established, that for adhoc query processing has not yet adequately understood. SDC-I proved that a parallel machine could attain significant performance improvements over a coventional sequential machine through the exploitation of the high degree of parallelism present in relational query processing. A unique bucket spreading parallel hash join algorithm is employed in SDC, which makes the system very robust in the presense of data skew and allows SDC to attain almost linear performance scalability. SDC adopts a hybrid parallel architecture, where globally it is a shared nothing architecture, that is, modules are connected through the multistage network, but each module itself is a symmetric multiprocessor system. Although most of the hardware elements use commodity microprocessors for improved performance to cost, only the interconnection network incorporates the special function to support our parallel relational algorithm. Data movement over the memory and the network, rather than computation, is heavy for I/O intensive database processing. A dedicated software system was carefully designed for efficient data movement. The implemented prototype consists of two modules. Its hardware and software organization is described. The performance monitoring tool was developed to visualize the system activities, which showed that SDC-I works very efficiently.

This paper discusses a digital neuroprocessor named Quantizer Neuron Chip (QNC) employing the Quantizer Neuron model and two newly developed schemes; "concurrent processing of quantizer neuron" and "removal of ineffective calculations". QNC simulates neural networks named the Multi-Functional Layered Network (MFLN) with 64 output neurons, 4672 quantizer neurons and two million synaptic weights and can be used for character or image recognition and learning. The processing speed of the chip achieved 1.6 µseconds per output neuron for recognition and 20 million connections updated per second (MCUPS) for learning. In addition, QNC can execute multichip operation for increasing the size of networks. We applied QNC to handwritten numeral recognition and realized high speed recognition and learning. QNC is implemented in a 1.2 µm double metal CMOS with sea of gates' technology and contains 27,000 gates on a 10.9910.93 mm2 chip.

A method for extracting and recognizing character strings from unformed document images, which have inclined character strings and have no structure at all, is described. To process such kinds of unformed documents, previous schemes, which are intended only to deal with documents containing nothing but horizontal or vertical strings of characters, do not work well. Our method is based on the idea that the processes of recognition and extraction of character patterns should operate together, and on the characteristic that the character patterns are located close to each other when they belong to the same string. The method has been implemented and applied to several images. The experimental results show the robustness of our method.

An automatic zip code recognition system for Japanese mail is proposed in this paper. It is assumed that a zip code is composed of three numerals and requited to be written in a specified frame. In actual images, however, the three numerals sometimes extend outside the specified frame and are not clearly separated. Considering this situation, the authors devised a system with two stages, the segmentation stage and the recognition stage. The segmentation stage consists of five steps: setting and adjusting of initial areas for numeral images (figures), calculation of the center of gravity of each figure, search for the horizontal and vertical boundaries of each figure, determination of the final area for each figure, and normalization of the figure in each final area. In the recognition stage, the Localized Arc Pattern Method (Arc method) proposed by Yoshimura et al. (1991) is implemented hierarchically; that is, a simple Arc method is applied first to each figure and a more complex one is applied subsequently unless the figure is identified in the first step. In the recognition process, every figure is judged as a numeral or otherwise rejected. The proposed system was applied to a database provided by the Institute for Post and Telecommunications Policy (IPTP). The segmentation algorithm yielded an adequate result. The recognition algorithm yielded scores as high as 90.6% in correct recognition rate and 0.7% in error rate. The best score of the precision index (P-index) specified by the IPTP was as low as 15.7 for the above mentioned IPTP database, while the score for another IPTP database was 16.9.