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  • The Improvement of Compositional Distribution in Depth and Surface Morphology of YBa2Cu3O7-δ-SrTiOx Multilayers

    Chien Chen DIAO  Gin-ichiro OYA  

     
    PAPER-HTS

      Vol:
    E77-C No:8
      Page(s):
    1209-1217

    Almost stoichiometric YBa2Cu3O7-δ(110) or (103) and SrTiOx(110) films, and multilayer films consisting of them have successfully been grown epitaxially on hot SrTiO3 substrates by 90off-axis rf magnetron sputtering with facing targets. Their whole composition, compositional distribution in depth, crystallinity and surface morphology were examined by inductively coupled plasma spectroscopy, Auger electron spectroscopy, reflection high-energy electron diffraction, and scanning tunneling microscopy or atomic force microscope, respectively. When any YBa2Cu3O7-δ film was exposed to air after deposition, a Ba-rich layer was formed in a near surface region of the film. However, such a compositional distribution in depth of the film was improved by in situ deposition of a SrTiOx film on it. Moreover, the surface roughness of the YBa2Cu3O7-δ film was improved by predeposition of a SrTiOx film under it. On the basis of these results, both YBa2Cu3O7-δ/SrTiOx/YBa2Cu3O7-δ/SrTiO3(sub.) and YBa2Cu3O7-δ/SrTiOx/YBa2Cu3O7-δ/SrTiOx/SrTiO3(sub.) multilayer films with average surface roughness of 3 nm were grown reproducibly, which had uniform compositional distribution throughout the depth of the film except a near surface region of the top YBa2Cu3O7-δ layer. A new 222 structure described by Sr8Ti8O20 (Sr2Ti2O5) with a long range ordered arrangement of oxygen vacancies was formed in the SrTiOx films deposited epitaxially on YBa2Cu3O7-δ films.

  • Sub-Halfmicron Flash Memory Technologies

    Koji SAKUI  Fujio MASUOKA  

     
    INVITED PAPER-Non-volatile Memory

      Vol:
    E77-C No:8
      Page(s):
    1251-1259

    This paper presents the history of Flash memories and the basic concept of their functions and also reviews a variety of Flash EEPROM's so far. As Flash memories have two influential features, non-volatility and low cost per bit, they are expected to become a driving force after DRAM's to support the semiconductor industry for the next thirty years, replacing hard and floppy disks which have a large market.

  • Distortion-Complexity and Rate-Distortion Function

    Jun MURAMATSU  Fumio KANAYA  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1224-1229

    We define the complexity and the distortion-complexity of an individual finite length string from a finite set. Assuming that the string is produced by a stationary ergodic source, we prove that the distortion-complexity per source letter and its expectation approximate arbitrarily close the rate-distortion function of this source as the length of the string grows. Furthermore, we apply this property to construct a universal data compression scheme with distortion.

  • A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories

    Kohji KANAMORI  Yosiaki S. HISAMUNE  Taishi KUBOTA  Yoshiyuki SUZUKI  Masaru TSUKIJI  Eiji HASEGAWA  Akihiko ISHITANI  Takeshi OKAZAWA  

     
    PAPER-Non-volatile Memory

      Vol:
    E77-C No:8
      Page(s):
    1296-1302

    A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are8 V and 12 V, respectively. The use of low positive internal-voltages results in reducing total process step numbers compared with reported memory cells. The HiCR cell also realizes low power and fast random access with a single 3 V power-supply.

  • Delay Analysis of Continuous ARQ Schemes with Markovian Error Channel

    Yukuo HAYASHIDA  Masaharu KOMATSU  

     
    PAPER-Communication Theory

      Vol:
    E77-B No:8
      Page(s):
    1023-1031

    Go-Back-N automatic repeat request (GBN ARQ) and Stop-and wait (SW) ARQ schemes are one of fundamental and widely used error control procedures for data communication and computer communication systems. The throughput and delay performances of these ARQ schemes have been analyzed for a random error channel, which could not applicable for a radio channel, for example. In this paper, considering the correlated, noisy channel, we derive the exact formula for the delay of a frame in GBN and SW ARQ schemes. First, the delay formula for the discrete time M[x]/G/1 queueing system with starter. Next, the virtual service time of a frame is found in terms of the decay factor of a two-state Markov chain. As a result, it is shown that the performance of the delay is improved with the larger decay factor.

  • A Resistor Coupled Josephson Polarity-Convertible Driver

    Shuichi NAGASAWA  Shuichi TAHARA  Hideaki NUMATA  Yoshihito HASHIMOTO  Sanae TSUCHIDA  

     
    PAPER-LTS

      Vol:
    E77-C No:8
      Page(s):
    1176-1180

    A polarity-convertible driver is necessary as a basic component of several Josephson random access memories. This driver must be able to inject a current having positive or negative polarity into a load transmission line such as a word or bit line of the RAM. In this paper, we propose a resistor coupled Josephson polarity-convertible driver which is highly sensitive to input signals and has a wide operating margin. The driver consists of several Josephson junctions and several resistors. The input signal is directly injected to the driver through the resistors. The circuit design is discussed on the operating principle of the driver. The driver is fabricated by 1.5 µm Nb technology with Nb/AlOx/Nb Josephson junctions, two layer Nb wirings, an Nb ground plane, Mo resistors, and SiO2 insulators. The Nb/AlOx/Nb Josephson junctions are fabricated using technology refined for sub-micron size junctions. The insulators between wirings are formed using bias sputtering technique to obtain good step coverage. The driver circuit size is 53 µm34 µm. Measurements are carried out at 10 kHz to quasistatically test the polarity-convertible function and the operating margin of the driver. Proper polarity-convertible operation is confirmed for a large operating bias margin of 70% at a fairly small input current of 0.3 mA.

  • Analysis of an Open-Ended Waveguide as a Probe for Near Field Antenna Measurements by Using TLM Method

    Yoshiyuki FUJINO  Cheuk-yu Edward TONG  

     
    PAPER-Antennas and Propagation

      Vol:
    E77-B No:8
      Page(s):
    1048-1055

    To increase the accuracy of a near field antenna measurement system, it is necessary to know radiation characteristics of a probe to detect near field data. Open ended waveguide used as a near field probe in our system was analyzed using Transmission Line Matrix (TLM) method which is a time domain electromagnetic solver. Validity of this analysis has been confirmed by comparison with experimental data and existing theoretical approximation. Frequency dependence of a complex reflection coefficient at the waveguide aperture has been derived and is shown to agree with measured values. The radiation pattern of the open ended waveguide with mounting structure is also calculated. Ripples on both the amplitude and phase patterns are correctly predicted by our simulation. This method can be applied to accurately model the effect of probe antennas to enhance the accuracy of near field antenna range.

  • A Capacitor-Error-Free SC Voltage Inverter with Zero Sensitivity to Element-Value Variations

    Sin Eam TAN  Takahiro INOUE  Fumio UENO  

     
    LETTER-Switched Capacitor Circuits

      Vol:
    E77-A No:8
      Page(s):
    1407-1408

    A capacitor-error-free SC voltage inverter with zero sensitivity to element-value variations is proposed. By virtue of the capacitor-error-free property, this SC voltage inverter is free from the capacitor mismatch. The performance of this SC voltage inverter has been confirmed from both the simulation and experiment.

  • High Speed DRAMs with Innovative Architectures

    Shigeo OHSHIMA  Tohru FURUYAMA  

     
    INVITED PAPER-DRAM

      Vol:
    E77-C No:8
      Page(s):
    1303-1315

    The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

  • A Bipolar-Based 0.5 µm BiCMOS Technology on Bonded SOI for High-Speed LSIs

    Makoto YOSHIDA  Toshiro HIRAMOTO  Tsuyoshi FUJIWARA  Takashi HASHIMOTO  Tetsuya MURAYA  Shigeharu MURATA  Kunihiko WATANABE  Nobuo TAMBA  Takahide IKEDA  

     
    PAPER-General Technology

      Vol:
    E77-C No:8
      Page(s):
    1395-1403

    A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

  • 3-D Object Recognition Using Hopfield-Style Neural Networks

    Tsuyoshi KAWAGUCHI  Tatsuya SETOGUCHI  

     
    PAPER-Bio-Cybernetics and Neurocomputing

      Vol:
    E77-D No:8
      Page(s):
    904-917

    In this paper we propose a new algorithm for recognizing 3-D objects from 2-D images. The algorithm takes the multiple view approach in which each 3-D object is modeled by a collection of 2-D projections from various viewing angles where each 2-D projection is called an object model. To select the candidates for the object model that has the best match with the input image, the proposed algorithm computes the surface matching score between the input image and each object model by using Hopfield nets. In addition, the algorithm gives the final matching error between the input image and each candidate model by the error of the pose-transform matrix proposed by Hong et al. and selects an object model with the smallest matching error as the best matched model. The proposed algorithm can be viewed as a combination of the algorithm of Lin et al. and the algorithm of Hong et al. However, the proposed algorithm is not a simple combination of these algorithms. While the algorithm of Lin et al. computes the surface matching score and the vertex matching score berween the input image and each object model to select the candidates for the best matched model, the proposed algorithm computes only the surface matching score. In addition, to enhance the accuracy of the surface matching score, the proposed algorithm uses two Hopfield nets. The first Hopfield net, which is the same as that used in the algorithm of Lin et al., performs a coarse matching between surfaces of an input image and surfaces of an object model. The second Hopfield net, which is the one newly proposed in this paper, establishes the surface correspondences using the compatibility measures between adjacent surface-pairs of the input image and the object model. the results of the experiments showed that the surface matching score obtained by the Hopfield net proposed in this paper is much more useful for the selectoin of the candidates for the best matched model than both the sruface matching score obtained by the first Hopfield net of Lin et al. and the vertex matching score obtained by the second Hopfield net of Lin et al. and, as the result, the object recognition algorithm of this paper can perform much more reliable object recognition than that obtained by simply combining the algorithm of Lin et al. and the algorithm of Hong et al.

  • Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories

    Hiroshi ONODA  Yuichi KUNORI  Kojiro YUZURIHA  Shin-ichi KOBAYASHI  Kiyohiko SAKAKIBARA  Makoto OHI  Atsushi FUKUMOTO  Natsuo AJIKA  Masahiro HATANAKA  Hirokazu MIYOSHI  

     
    PAPER-Non-volatile Memory

      Vol:
    E77-C No:8
      Page(s):
    1279-1286

    A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm2 cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm2 cell size for a 0.5 µm 64 Mbit flash memory, is described.

  • High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM

    Toshikazu SUZUKI  Toru IWATA  Hironori AKAMATSU  Akihiro SAWADA  Toshiaki TSUJI  Hiroyuki YAMAUCHI  Takashi TANIGUCHI  Tsutomu FUJITA  

     
    PAPER-DRAM

      Vol:
    E77-C No:8
      Page(s):
    1334-1342

    Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

  • An 8-Dimensional Trellis-Coded 8-PSK with Non-zero Crossing Constraint

    Tadashi WADAYAMA  Koichiro WAKASUGI  Masao KASAHARA  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1274-1280

    We present an 8-dimensional trellis-coded 8-PSK with a symbol transition constraint that is similar to that of π/4-shift quadrature phase shift keying (QPSK). This scheme can achieve a coding gain of 1.6 to 2.4 dB at the same rate of π/4-shift QPSK on Gaussian channel, and it has also an immunity against the integer multiples of 90 phase ambiguities. In order to label the constellation of the proposed scheme, a constellation partitioning algorithm is presented. This algorithm, on the basis of set partitioning, can be used to label the signal constellation with no coset structure.

  • Ultrafast Single-Shot Water and Fat Separated Imaging with Magnetic Field Inhomogeneities

    Shoichi KANAYAMA  Shigehide KUHARA  Kozo SATOH  

     
    PAPER-Medical Electronics and Medical Information

      Vol:
    E77-D No:8
      Page(s):
    918-924

    Ultrafast MR imaging (e.g., echo-planar imaging) acquires all the data within only several tens of milliseconds. This method, however, is affected by static magnetic field inhomogeneities and chemical shift; therefore, a high degree of field homogeneity and water and fat signal separation are required. However, it is practically impossible to obtain an homogeneous field within a subject even if in vivo shimming has been performed. In this paper, we describe a new ultrafast MR imaging method called Ultrafast Single-shot water and fat Separated Imaging (USSI) and a correction method for field inhomogeneities and chemical shift. The magnetic field distribution whthin the subject is measured before thd scan and used to obtain images without field inhomogeneity distortions. Computer simulation results have shown that USSI and the correction method can obtain water and fat separated images as real and imaginary parts, respectively, of a complex Fourier transform with a single-shot scan. Image quality is maintained in the presence of field inhomogeneities of several ppm similar to those occurring under practical imaging conditions. Limitations of the correction method are also discussed.

  • LiNbO3 Optical Modulator Using a Superconducting Resonant Electrode

    Keiji YOSHIDA  Akihiko NOMURA  Yutaka KANDA  

     
    PAPER-LTS

      Vol:
    E77-C No:8
      Page(s):
    1181-1184

    Microwave characteristics of a LiNbO3 optical modulator using a superconductor (Pb-In-Au) as a resonant electrode has been studied experimentally at low temperatures down to 4.2 K. It is shown that at the resonance frequency of 14.8 GHz the obtained modulation depth takes a maximum value as expected from theory when the electrode becomes superconducting. The present results demonstrate the possible applications of superconducting electrodes to high performance LiNbO3 optical modulators.

  • Efficient Cryptosystems over Elliptic Curves Based on a Product of Form-Free Primes

    Hidenori KUWAKADO  Kenji KOYAMA  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1309-1318

    This paper proposes RSA-type cryptosystems over elliptic curves En(O, b) and En(a, O),where En(a, b): y2 x3+ax+b (mod n),and n is a product of from-free primes p and q. Although RSA cryptosystem is not secure against a low exponent attack, RSA-type cryptosystems over elliptic curves seems secure against a low multiplier attack. There are the KMOV cryptosystem and the Demytko cryptosystem that were previously proposed as RSA-type cryptosystems over elliptic curves. The KMOV cryptosystem uses form-restricted primes as p q 2(mod 3)or p q 3(mod 4), and encrypts/decrypts a 2log n-bit message over varied elliptic curves by operating values of x and y coordinates. The Demytko cryptosystem, which is an extension of the KMOV cryptosystem, uses form-free primes, and encrypts/decrypts a log n-bit message over fixed elliptic curves by operating only a value of x coordinates. Our cryptosystems, which are other extensions fo the KMOV cryptosystem, encrypt/decrypt a 2log n-bit message over varied elliptic curves by operating values of x and y coordinates. The Demytko cryptosystem and our cryptosystems have higher security than the KMOV cryptosystem because from-free primes hide two-bit information about prime factors. The encryption/decryption speed in one of our cryptosystems is about 1.25 times faster than that in the Demytko cryptosystem.

  • A Secure Broadcast Communication Method with Short Messages

    Masahiro MAMBO  Akinori NISHIKAWA  Eiji OKAMOTO  Shigeo TSUJII  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1319-1327

    Broadcasting with secrecy of messages is important in a situation such as pay television. In pay television only a broadcasting station broadcasts a message. On the other hand, broadcast communication is also important. Broadcast communication means any user in a whole group can broadcast a message to any subset of the group. In this paper the efficiency of secure broadcast communication is discussed in terms of the length of messages sent and the encryption speed. We prove that the length of the broadcast messages is not kept less than O(n), where n is the number of receivers, when a broadcast system has a form of a single system which is defined as the generalized form of an individual key method and a master key method. In contrast, the proposed secure broadcast communication method, a multi-dimension method, keeps the length of messages sent O(mmn), where m is the number of the dimension used in the multi-dimension method. At the same time the encryption speed was reduced from O(n(log(n+C2)+C3)) of the master key method to O(mn(logmn+C1)) of the multi-dimension method.

  • Performance Analysis of Multi-Pulse Pulse Position Modulation (MPPM) in Noisy Photon Counting Channel

    Tomoaki OHTSUKI  Iwao SASASE  Shinsaku MORI  

     
    LETTER

      Vol:
    E77-A No:8
      Page(s):
    1381-1386

    We analyze the error probability performance of multi-pulse pulse position modulation (MPPM) in noisy photon counting channel. Moreover we investigate the error perofrmance of convolutional coded MPPM and RS coded MPPM in noisy photon counting channel. We define a distance between symbols as the number of nonoverlapping pulses in one symbol, and by using the distance we analyze the error performance of MPPM in noisy photon counting channel. It is shown that MPPM has better performance than PPM in the error probability performance in noisy photon counting channel. For PPM in noisy photon counting channel, convolutional codes are more effective than RS codes to reduce the average transmitting power. For MPPM in noisy photon counting channel, however, RS codes are shown to be more effective than convolutional codes.

  • Low-Voltage and Low-Power ULSI Circuit Techniques

    Masakazu AOKI  Kiyoo ITOH  

     
    INVITED PAPER-General Technology

      Vol:
    E77-C No:8
      Page(s):
    1351-1360

    Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

37861-37880hit(42756hit)