We propose an advanced DRAM array driving technique which can achieve low-voltage operation, which we call a well-synchronized sensing and equalizing method. This method sets the DRAM array free from the body effect, achieves a small influence of the short channel effect, and reduces the leakage current. The sense and restore amplifier and equalizer can operate rapidly under a low-voltage operating condition such as 1.0 V Vcc. Therefore, we can make determining the Vth easy for the satisfaction of the high-speed, the low-power dissipation, and a simple device structure. The well-synchronized sensing and equalizing method is applicable to low-voltage operating DRAM's with capacity of 256 Mbits and more.

Analog switched-capacitor memory circuits are suitable for use in a wide range of applications where analog waveforms must be captured or delayed, such as the recording of pulse echo events and pulse shapes. Analog sampling systems based on switched-capacitor techniques offer performance superior to that of flash A/D converters and charge-coupled devices with respect to cost, density, dynamic range, sampling speed, and power consumption. This paper proposes an architecture with which sampling frequencies of several hundred megahertz can be achieved using conventional CMOS technology. Issues concerning the design and implementation of an analog memory circuit based on the proposed architecture are presented. An experimental two-channel memory with 32 sampling cells in each channel has been integrated in a 2-µm CMOS technology with poly-to-poly capacitors. The measured nonlinearity of this prototype is 0.03% for a 2.5 V input range, and the memory cell gain matching is 0.01% rms. The dynamic range of the memory exceeds 12 b for a sampling frequency of 700 MHz. The power dissipation for one channel operated from a single 5 V supply is 2 mW.

An efficient back-bias (Vbb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a Vbb level of 1.44 V at Vcc1.5 V, compared to a conventional system in which Vbb only reaches 0.6 V. HPC can pump without the threshold voltage (Vth) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAM's, because a Vbb level lower than 1.0 V is necessary to meet the limitations of the Vth of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.

A monolithic active equalizer in 2-µm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations.

The design of an asynchronous digital sample-rate converter for digital-audio applications is presented. The theory of asynchronous sample-rate conversion is discussed using a signal-processing model that is based on highly interpolated input samples. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each output sample. Sample-rate ratio changes of up to 2:1 in either direction can be accommodated. The proposed signal-processing algorithm has been implemented in a 0.8-µm CMOS technology. Measurement results show excellent agreement with theory.

An adaptive array antenna can be considered as a useful tool of combating with fading in mobile communications. We can directly obtain the optimal weight coefficients without updating in temporal sampling, if the arrival angles and signal-to-noise ratio (SNR) of the desired and the undesired signals can be accurately estimated. The Maximum Entropy Method (MEM) can estimate the arrival angles, and the SNR from spatially sampled signals by an array antenna more precisely than the Discrete Fourier Transform (DFT). Therefore, this paper proposes and investigates an adaptive array antenna based on spatial spectral estimation using MEM. We call it MEM array. In order to reduce complexity for implementation, we also propose a modified algorithm using temporal updating as well. Furthermore, we propose a method of both improving estimation accuracy and reducing the number of antenna elements. In the method, the arrival angles can be approximately estimated by using temporal sampling instead of spatial sampling. Computer simulations evaluate MEM array in comparison with DFT array and LMS array, and show improvement owing to its modified algorithm and performance of the improved method.

This paper reviews recent progress in adaptive signal processing techniques for digital mobile radio communications. In Radio Signal Processing (RSP) , digital signal processing is becoming more important because it makes it relatively easy to develop sophisticated adaptive processing techniques, Adaptive signal processing is especially important for carrier signal processing in RSP. Its main objective is to realize optimal or near-optimal radio signal transmission. Application environments of adaptive signal processing in mobile radio are clarified. Adaptive equalization is discussed in detail with the focus on adaptive MLSE based on the blind algorithm. Demodulation performance examples obtained by simulations and experiments are introduced, which demonstrates the recent advances in this field. Next, new trends in adaptive array processing, interference cancelling, and orthogonalization processing are reviewed. Finally, the three automatic calibration techniques that are based on adaptive signal processing are described for realizing high precision transmission devices.

We develop a convergence theory of the simple genetic algorithm (SGA) for two-bit problems (Type I TBP and Type II TBP). SGA consists of two operations, reproduction and crossover. These are imitations of selection and recombination in biological systems. TBP is the simplest optimization problem that is devised with an intention to deceive SGA into deviating from the maximum point. It has been believed that, empirically, SGA can deviate from the maximum point for Type II while it always converges to the maximum point for Type I. Our convergence theory is a first mathematical achievement to ensure that the belief is true. Specifically, we demonstrate the following. (a) SGA always converges to the maximum point for Type I, starting from any initial point. (b) SGA converges either to the maximum or second maximum point for Type II, depending upon its initial points. Regarding Type II, we furthermore elucidate a typical sufficient initial condition under which SGA converges either to the maximum or second maximum point. Consequently, our convergence theory establishes a solid foundation for more general GA convergence theory that is in its initial stage of research. Moreover, it can bring powerful analytical techniques back to the research of original biological systems.

This paper proposes a digitalized quadrature modulator for burst-by-burst carrier frequency hopping in TDMA-TDD systems. It employs digital frequency synthesis and a multiplexing modulation scheme to give the frequency offset to the modulated IF signal. Moreover, to reduce the frequency settling time of the RF synthesizer below the guard time duration, a phase and frequency preset (PFP) PLL synthesizer is employed. By employing the digital modulation scheme, the proposed modulator needs only one D/A converter, as a result, the complexity of adjusting the DC offset and amplitude between analog signals of the in-phase and the quadrature phase is eliminated. The performance of the proposed modulator is analyzed theoretically and simulated by computers. Theoretical analyses show that the frequency settling time with 15MHz hopping width in the 1900MHz band is reduced by more than 75% from that of the conventional synthesizer. The settling time is less than 40µs which is shorter than the typical guard time of the burst signal format. The analyses also show that the power consumption of the proposed modulator is lower than that of the conventional modulator employing a full band digital frequency converter. Furthermore, the computer simulation confirms that the power spectra and the constellations of the proposed modulator for the coherent and the π/4-shift QPSK modulation schemes can be successfully generated.

This letter proposes a high speed multifiber connector assembly method, which uses UV-curable adhesive and which does not require a polishing process, thus reducing the connector assembly time. It is confirmed that the assembly time can be reduced to less than half the time required with the conventional assembly method. The multifiber connectors assembled using this method have a low connection loss and stable mechanical characteristics.

A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 µm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 µs.

A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the emitter-follower input from the logic stage. Simulation results based on a 0.5-µm advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively.

A 16-Mb flash EEPROM has been developed based on the 0.6-µm triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 µm1.7 µm, and the die size has resulted in 7.7 mm17.32 mm.

This paper proposes using an adaptive array in a base station for signal reception and transmission in order to increase the spectral efficiency without decreasing the cell radius. The adaptive array controls the directivity pattern of the base station to reduce co-channel interference during reception; the same array pattern is applied during transmission to prevent unnecessary illumination. Computer simulation results show that the cluster size can be reduced to one with time division duplexing (TDD), indicating that we can reuse the same frequency group at all cells. Thus, the improvement in spectral efficiency is as much as 16 fold that of an omni-antenna. Moreover, load sharing, which is expected to improve the channel utilization for unbalanced load situations, is available by cell overlapping. Frequency division duplexing (FDD) requires a weight adjust function to be applied for transmission since the difference in frequency between signal reception and transmission causes null positioning error. However, simple LMS-adjusting can provide a cluster size of one as well as cell overlapping when the frequency deference is 5%.

A new reference voltage generator with ultralow standby current of less than 1 µA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-µm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/ from room temperature to 100, and output noise of less than 12 mV for 1 Vp-p Vcc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAM's with low active and data-retention currents comparable to SRAM's.

The paper proposes a new multicarrier 16QAM system for high-quality and high-bit-rate transmission with high spectral efficiency in land mobile radio communications. The proposed system uses a multicarrier transmission scheme to provide immunity against frequency-selective fading distortion. It also uses pilot-symbol-aided 16QAM to increase spectral efficiency, and it combines space diversity and FEC with maximum likelihood decoding to improve the bit error rate (BER) performance. Computer simulation shows that a BER of less than 10-4 is obtained over frequency-selective fading channels with rms delay spread of less than 5.4µs. Using a bandwidth of 200kHz the proposed system can achieve high-quality transmission with a total information rate of 256kbit/s.

This paper proposes a new strategy for reducing contention for a critical section in a multiprocessor system and shows that the strategy can improve CPU utilization by several percent. Using simulation and queueing theory, it also discusses when the strategy is superior to conventional ones.

The generation and design of a stationary Markov signal are discussed as an inverse problem, in which one looks for a transition probability when a stationary probability distribution is given. This paper presents a new solution to the inverse problem, which makes it possible to design and generate a Markov random signal with arbitrary probability distribution and an exponential correlation function. Several computer results are illustrated in figures.

The optical waveguides containing phthalocyanine as an optically active material were fabricated and transmission properties were investigated experimentally and numerically. The positive refractive index change was observed in the glass waveguide with a vanadyl phthalocyanine thin film as a top layer. The thermal influence on refractive index change was estimated by surface plasmon measurements.

This paper introduces some modelling methods of time-varying stochastic process and its linear/nonlinear adaptive identification. Time-varying models are often identified by using a least square criterion. However the criterion should assume a time invariant stochastic model and infinite observed data. In order to adjust these serious different assumptions, some windowing techniques are introduced. Although the windows are usually applied to a batch processing of parameter estimates, all adaptive methods should also consider them at difference point of view. In this paper, two typical windowing techniques are explained into adaptive processing. In addition to the use of windows, time-varying stochastic ARMA models are built with these criterions and windows. By using these criterions and models, this paper explains nonlinear parameter estimation and the property of estimation convergence. On these discussions, some approaches are introduced, i.e., sophisticated stochastic modelling and multi-rate processing.