In this paper, symbols and numerals in topographic maps are recognized by the multi-angled parallelism (MAP) matching method, and small dots and lines are extracted by the MAP operation method. These results are then combined to determine the value, position, and attributes of elevation marks. Also, we reconstruct three dimensional surfaces described by contours, which is difficult even for humans since the elevation symbols are sparse. In reconstruction of the surface, we define an energy function that enfores three constraints: smoothness, fit, and contour. This energy function is minimized by solving a large linear system of simultaneous equations. We describe experiments on 25,000:1 scale topographic maps of the Tsukuba area.

An integrated pen interface system was developed to allow effective Japanese text entry. It consists of sub-systems for handwriting recognition, contextual post-processing, and enhanced Kana-to-Kanji conversion. The recognition sub-system uses a hybrid algorithm consisting of a pattern matcher and a neural network discriminator. Special care was taken to improve the recognition of non-Kanji and simple Kanji characters frequently used in fast data entry. The post-processor predicts consecutive characters on the basis of bigrams modified by the addition of parts of speech and substitution of macro characters for Kanji characters. A Kana-to Kanji conversion method designed for ease of use with a pen interface has also been integrated into the system. In an experiment in which 2,900 samples of Kanji and non-Kanji characters were obtained from 20 subjects, it was observed that the original recognition accuracy of 83.7% (the result obtained by using the pattern matching recognizer) was improved to 90.7% by adding the neural network discriminator, and that it was further improved to 94.4% by adding the post-processor. The improved recognition accuracy for non-Kanji characters was particularly marked.

This paper proposes a new, high-speed method of filling in the contours of alpha-numeric characters to produce correct binary image patterns. We call this method the improved edge-fill method because it improves on a previously developed edge-fill method. Ambiguity of the conventional edge-fill method on binary images are eliminated by selecting fill pixels from combinations of Freeman's chain code, which expresses contour lines. Consequently, the areas inside the contour lines are filled in rapidly and correctly. With the new method, the processing time for character image generation is reduced by ten to tewnty percent over the conventional method. The effectiveness of the new method is examined in experiments using both Arabic numerals and letters from the Roman alphabet. Results show that this fill method is able to produce correct image patterns and that it can be applied to alpha-numeric-character contour filling.

A 250-MIPS, 125-MFLOPS peak performance processing element (PE), which is being developed for an on-chip multiprocessor, has been modeled and evaluated. The PE includes the following new architecture components: an FPU shared by several IUs in order to increase the efficiency of the FPU pipelines, an on-chip data cache with a prefetch mechanism to reduce clock cycles waiting for memory, and an interface to high speed DRAM, such as Rambus DRAM and Synchronous DRAM. As a result, a PE model with an FPU shared by four or eight IUs causes only 10% performance reduction compared to a model with an un-shared FPU model while saving the cost of three FPUs. Furthermore, a PE model with prefetch operates 1.2 to 1.8 times faster than a model without prefetch at 250-MHz clock rate when the Rambus DRAM is connected. It becomes clear that this PE architecture can bring a high effective performance at over 250-MHz, and is cost-effective for the on-chip multiprocessor.

In this paper, we propose DSVMA (Data Steal into Voice Multiple Access) scheme for integration of voice and data in wireless information networks. By using speech activity detectors and effective downstream control signals, DSVMA enables data terminals to transmit multi-packet messages when voice terminals are in silent periods. The S-G (throughput versus offered load) performance of the DSVMA system and the blocking probabilities of both the second generation systems and the DSVMA systems are evaluated by the static analysis. A dynamic analysis of a system with finite number of terminals is also presented using an approximate Markov analysis method. Some numerical examples are given in the paper. As a result, it is shown that DSVMA can improve the channel utility efficiency of a circuit-switched TDMA (Time Division Multiple Access) wireless communication system and is directly applicable for second generation wireless information systems.

The ultimate minimum energy of switching mechanism for MOS integrated circuits have been studied. This report elucidates the evaluation methods for minimum switching energy of instantaneous discharged mechanism after charging one, namely, recycled energy of the MOS device. Two approaches are implemented to capture this concept. One is a switching energy by the time-dependent gate capacitance (TDGC) model ; the other one by results developed by transient device simulation, which was implemented using Finite Element Method (FEM). It is understood that the non-recycled minimum swhiching energies by both approaches show a good agreement. The recycled energies are then calculated at various sub-micron gate MOS/SOI devices and can be ultra-low power of the MOS integrated circuits, which may be possible to build recycled power circuitry for super energy-saving in the future new MOS LSI. From those results, (1) the TDGC is simultaneously verified by consistent match of the non-recycled minimum switching energies; (2) the recycled switching energy is found to be the ultimate lower bound of power for MOS device; (3) the recycled switching energy can be saved up to around 80% of that of current MOS LSI.

This paper proposes a waveguide type optical amplifier which is constructed in 1.3 at.% Nd doped yttrium gallium garnet thin films deposited on yttrium aluminum garnet substrates by using RF sputtering . The crystalline thin film with a satisfactory stoichiometric composition is obtained by annealing at 1000 after depositing at 600. The spectral properties and the optical amplification characteristics of the thin film waveguide are measured. Optical propagation loss of 2.2 dB/cm is achieved at the wavelength of 1061.5 nm. Absorption peak of the thin film is located at 808 nm, and fluorescence peaks at about 1.06 µm and 1.3 µm suggest the possibility of optical amplification. For the wavelength of 1061.5 nm, a maximum gain of 4.4 dB and a S/N ratio of 12.6 dB are obtained at a signal power of 10 µW and the pump power of about 14 mW. The pump efficiency is more than 0.3 dB/mW.

This paper examines a novel digital modulation/multiple access technique called Multi-Carrier Code Division Multiple Access (MC-CDMA) where each data symbol is transmitted at multiple narrowband subcarriers. Each subcarrier is encoded with a phase offset of 0 or π based on a spreading code. Analytical results are presented on the performance of this modulation scheme in an indoor wireless multipath radio channel.

In digital control, it is essential to make the delay time for a large number of multiply-additions small because of sensor feedback. To meet the requirement, an architecture of the reconfigurable parallel processor using field-programmable gate arrays (FPGAs) is proposed. Although the performance is drastically increased in the full custom VLSI implementation, even the reconfigurable parallel processor using FPGAs becomes useful for many practical digital control applications. The performance evaluation shows that the delay time for the resolved acceleration cotrol computation of a twelve-degrees-of-freedom (DOF) redundant manipulator becomes about 70 µs which is about seventeen times faster than that of a parallel processor approach using conventional digital signal processors (DSPs).

This paper proposes a request-grant-type multiple access control called bandwidth-request labeled-slot multiple access (BLMA) for wireless LANs. BLMA employs slotted ALOHA in the request stage and has an algorithm to avoid unfair access due to the capture effect in this stage. In BLMA, terminals transmit data using fixed length slots called fragment slots in the transmission stage. The base station assigns the fragment slots one by one to terminals for peer-to-peer communication in which terminals communicate directly. It also controls the retransmission based on the stop and wait automatic repeat request scheme. The base station retransmits data for the source terminal as much as it can. BLMA provides simple and fair access control, efficient link utilization, and easy implementation. It also allows modes to be easily changed automatically from peer-to-peer communication to store-and-forward communication in which terminals communicate via the base station. Design concepts of a wireless MAC discussed and details of BLMA are described. The evaluation results of the BLMA are also shown.

In this tutorial exposition, we present a discussion for the extended interpolation approximation with respect to a class of 1- or multi-dimensional signals. We will provide some conditions concerning to the convergence of the approximation signal to the original one. An exposition for the optimum interpolation is given with respect to a class of n-dimensional signals whose Fourier spectrums have the weighted L2 norms smaller than a given positive number. In this discussion, in the first phase, we present the outline of the approximation which minimizes the measure of error equal to the envelope of the approximation errors. Initially, it is assumed that the infinite number of interpolation functions with different functional forms are used in the approximation. However, the resultant optimum interpolation functions are expressed as the parallel shifts of the finite number of n-dimensional functions. It should be noted that the optimum interpolation functions presented in this tutorial exposition minimize wide variety of measures of error defined in each separate area in the space variable domain at the same time. Interesting reciprocal relation in the approximation, is discussed. An equivalent expression of the approximation formula in the frequency domain, is provided also. In this paper, we will also introduce the optimum approximation using space-limited analysis filters and interpolation functions with the infinite supports. This approximation satisfies beautiful orthogonal relation and minimizes various measure of error symultaneously including many types of measure of error defined in the frequency domain.

This paper proposes a semi-autonomous frame synchronization scheme for a TDMA (Time Division Multiple Access)-TDD (Time Division Duplexing) personal communication system to realize accurate frame synchronization in a simple manner. The proposed scheme selects specific adjacent base stations by the station indicator (SID), carries out high resolution frame timing control, and compensates the propagation delay between base stations by using geographical data. This autonomously synchronizes all base stations to each other. Computer simulation and analysis results confirm the accurate and stable TDMA frame synchronization of all base stations even in fading environments.

An asynchronous spread spectrum (SS) modem for 2.4-GHz wireless LAN has been implemented using an efficient ZnO-SiO2-Si surface acoustic wave (SAW) convolver. The design of the highly efficient SAW convolver was developed at Tohoku University and commercially manufactured by Clarion Co., Japan. The modem can operate under full-duplex transmission in the same frequency range of the 2.4-GHz SS band. The SS modem is based on a direct-sequence/code-shift-keying (DS/CSK) method for the modulation. Pseudo-noise (PN) codes are chosen from a preferred pair of 127-chip m-sequences and the code rate is 14MHz. The asynchronous demodulation is simply realized utilizing the coherent correlation characteristics of the SAW convolver. Under full-duplex transmission, the self-jamming caused by a transmitted signal in the modem itself is effectively reduced by an RF isolator and the SS processing gain. The implemented modem has been tested using a coaxial cable with attenuator. A bit error rate of 10-6 under full-duplex transmission is observed at 78.3dB of a desired to undesired signal ratio. The effective range is estimated on the basis of two-path propagation model. From self-jamming rejection of 78.3dB, the effective range under real-time full-duplex is estimated to be about 200m.

Stored channel simulation for mobile radio channel can be the common base of the development of future world wide personal radio communication systems, especially for high bit-rate digital system. This paper proposes a mobile radio channel database which is suitable for the laboratory channel simulation using a simple stored channel simulator, also proposed by the author. The database enables the establishment of a mobile radio channel database containing worldwide channel data in a few discs of compact disc.

A fuzzy microprocessor is developed using 1.2 µm CMOS process. The inference scheme for the if-then fuzzy rules consists of three main steps i. e. if-part process, then-part process and defuzzification. In order to realize very high-speed inference and moderate programmability, we introduce three-type different structures i.e. SIMD, logic-in-memory and Wallace tree structures which are suitable for the three main steps. The inference speed including defuzzification is 7.5 MFLIPS which is 12.9 times higher than the previous VLSI implementation, and it can carry out many rules (960 rules) and many input and output variables (16 variables).

In this paper we propose a method for increasing the reliability in multiprocessor realization of lowpass and highpass FIR digital filters possessing a maximally flat magnitude response. This method is based on the use of array realization of the filter which has been proposed earlier by the authors. It is shown that if a processing module of the array functions erroneously, it is possible to exclude the module and still obtain a lowpass FIR filter. However, as a price we should tolerate a slight degradation in the magnitude response of the filter that is equivalent to a wider transition band. We also analyze the behavior of the filter when our proposed schemes are implemented on more than one module. The justification of our approach is based on that a slight degradation of the spectral characteristics of a filter may be well tolerated in most filtering applications and thus a graceful degradation in the frequency domain can sufficiently reduce the vulnerability to errors.

A new frequency hopped spread spectrum system is introduced. The frequency hopped signal is a combination of multi frequency and multi phase signals and is referred to as Frequency Hopped/Joint Frequency-Phase Modulation (FH/JFPM). A noncoherent receiver for the FH/JFPM signals is introduced and an exact expression for the bit error rate is obtained. A performance analysis of this system is given in the presence of broadband and partial-band noise jamming. The optimal jamming strategy is evaluated. The results show that under these jamming conditions the FH/JFPM perform better than the FH/M-ary DPSK and FH/M-ary FSK systems. It is also shown that for a given channel bandwidth and data rate, the FH/JFPM system has more processing gain than its FSK or DPSK counterparts.

The paper describes the architecture and the simulated performances of a memory-based chip that emulates human cortical processing in early visual tasks, such as texture segregation. The featural elements present in an image are extracted by a convolution block and subsequently processed by the cortical chip, whose neurons, organized into three layers, gain relational descriptions (intelligent processing) through recurrent inhibitory/excitatory interactions between both inter-and intra-layer parallel pathways. The digital implementation of this architecuture directly maps the set of equations determining the status of the cortical network to achieve an optimal exploitation of VLSI technology in neural computation. Neurons are mapped into a memory matrix whose elements are updated through a programmable computational unit that implements synaptic interconnections. By using 0.5 µm-CMOS technology, full cortical image processing can be attained on a single chip (2020 mm2 die) at a rate higher than 70 frames/second, for images of 256256 pixels.