This paper addresses the attribute recognition problem, a field of research that is dominated by studies in the visible spectrum. Only a few works are available in the thermal spectrum, which is fundamentally different from the visible one. This research performs recognition specifically on wearable attributes, such as glasses and masks. Usually these attributes are relatively small in size when compared with the human body, on top of a large intra-class variation of the human body itself, therefore recognizing them is not an easy task. Our method utilizes a decomposition framework based on Robust Principal Component Analysis (RPCA) to extract the attribute information for recognition. However, because it is difficult to separate the body and the attributes without any prior knowledge, noise is also extracted along with attributes, hampering the recognition capability. We made use of prior knowledge; namely the location where the attribute is likely to be present. The knowledge is referred to as the Probability Map, incorporated as a weight in the decomposition by RPCA. Using the Probability Map, we achieve an attribute-wise decomposition. The results show a significant improvement with this approach compared to the baseline, and the proposed method achieved the highest performance in average with a 0.83 F-score.

In this paper, we introduce a self-constructive Normalized Gaussian Network (NGnet) for online learning tasks. In online tasks, data samples are received sequentially, and domain knowledge is often limited. Then, we need to employ learning methods to the NGnet that possess robust performance and dynamically select an accurate model size. We revise a previously proposed localized forgetting approach for the NGnet and adapt some unit manipulation mechanisms to it for dynamic model selection. The mechanisms are improved for more robustness in negative interference prone environments, and a new merge manipulation is considered to deal with model redundancies. The effectiveness of the proposed method is compared with the previous localized forgetting approach and an established learning method for the NGnet. Several experiments are conducted for a function approximation and chaotic time series forecasting task. The proposed approach possesses robust and favorable performance in different learning situations over all testbeds.

Recent research has shown that the class of rotation symmetric Boolean functions is beneficial to cryptographics. In this paper, for an odd prime p, two sufficient conditions for p-variable rotation symmetric Boolean functions to be 1-resilient are obtained, and then several concrete constructions satisfying the conditions are presented. This is the first time that resilient rotation symmetric Boolean functions have been systematically constructed. In particular, we construct a class of 2-resilient rotation symmetric Boolean functions when p=2m+1 for m ≥ 4. Moreover, several classes of 1-order correlation immune rotation symmetric Boolean functions are also got.

An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.

Permutation polynomials over Zpn are useful in the design of cryptographic algorithms. In this paper, we obtain an equivalent condition for polynomial functions over Zpn to be permutations, and this equivalent condition can help us to analysis the randomness of such functions. Our results provide a method to distinguish permutation polynomials from random functions. We also introduce how to improve the randomness of permutation polynomials over Zpn.

A floating-point multiplier with concurrent error detection capability by partial duplication is proposed. It uses a truncated multiplier for checking of the significand (mantissa) multiplication instead of full duplication. The proposed multiplier can detect any erroneous output with error larger than one unit in the last place (1 ulp) of the significand, which may be overlooked by residue checking. Its circuit area is smaller than that of a fully duplicated one. Area overhead of a single-precision multiplier is about 78% and that of a double-precision one is about 65%.

In this paper, we study the problem of noise with regard to the perfect reconstruction of non-bandlimited signals, the class of signals having a finite number of degrees of freedom per unit time. The finite rate of innovation (FRI) method provides a means of recovering a non-bandlimited signal through using of appropriate kernels. In the presence of noise, however, the reconstruction function of this scheme may become ill-conditioned. Further, the reduced sampling rates afforded by this scheme can be accompanied by increased error sensitivity. In this paper, to obtain improved noise robustness, we propose the matrix pencil (MP) method for sample signal reconstruction, which is based on principal component analysis (PCA). Through the selection of an adaptive eigenvalue, a non-bandlimited signal can be perfectly reconstructed via a stable solution of the Yule-Walker equation. The proposed method can obtain a high signal-to-noise-ratio (SNR) for the reconstruction results. Herein, the method is applied to certain non-bandlimited signals, such as a stream of Diracs and nonuniform splines. The simulation results demonstrate that the MP and PCA are more effective than the FRI method in suppressing noise. The FRI method can be used in many applications, including those related to bioimaging, radar, and ultrasound imaging.

Through-silicon via (TSV) assignment problem is one of the key design challenges of 3-D IC which is crucial to the wire length and signal delay. In this work we formulate the 3-D IC TSV assignment as an Integer Minimum Cost Multi Commodity (IMCMC) problem on a IMCMC network, and propose a multi-level algorithm. It coarsens the IMCMC network level by level, applies a rough flow assignment on each level of coarsened graph, and generates only promising edges to reduce the IMCMC network size. Benefiting from the multi-level structure, we propose a mixed single and multi commodity flow method improve the TSV assignment solution quality. Moreover, given a TSV assignment, we propose an extended layer by layer algorithm to further optimize the TSV assignment. The experimental results demonstrate that our multi-level with mixed single and multi commodity flow algorithm achieves not only smaller wire length but also shorter runtime compared to other existing works.

The differential fault analysis of SOSEMNAUK was presented in Africacrypt in 2011. In this paper, we improve previous work with algebraic techniques which can result in a considerable reduction not only in the number of fault injections but also in time complexity. First, we propose an enhanced method to determine the fault position with a success rate up to 99% based on the single-word fault model. Then, instead of following the design of SOSEMANUK at word levels, we view SOSEMANUK at bit levels during the fault analysis and calculate most components of SOSEMANUK as bit-oriented. We show how to build algebraic equations for SOSEMANUK and how to represent the injected faults in bit-level. Finally, an SAT solver is exploited to solve the combined equations to recover the secret inner state. The results of simulations on a PC show that the full 384 bits initial inner state of SOSEMANUK can be recovered with only 15 fault injections in 3.97h.

The problem of radar constant-modulus (CM) waveform design for the detection of multiple targets is considered in this paper. The CM constraint is imposed from the perspective of hardware realization and full utilization of the transmitter's power. Two types of CM waveforms — the arbitrary-phase waveform and the quadrature phase shift keying waveform — are obtained by maximizing the minimum of the signal-to-clutter-plus-noise ratios of the various targets. Numerical results show that the designed CM waveforms perform satisfactorily, even when compared with their counterparts without constraints on the peak-to-average ratio.

In this paper, we describe the fabrication of low leakage Superconductor/Insulator/Superconductor (SIS) junctions with a Nb/Al/AlOx/Al/Nb structure. In other words, an extra Al layer was added onto the top of the insulator in a conventional Nb/Al/AlOx/Nb junction. We measured the current and voltage (IV) characteristics of both the Nb/Al/AlOx/Al/Nb and Nb/Al/AlOx/Nb junctions at the temperature of liquid helium, and found that the sub-gap leakage current in the Nb/Al/AlOx/Al/Nb junctions was much lower than that of the Nb/Al/AlOx/Nb junctions. Our analysis of the IV characteristics indicates that the quality of the AlOx insulator used in the Nb/Al/AlOx/Al/Nb junction was close to ideal, while the insulator used in the Nb/Al/AlOx/Nb junction had possible defects. According to the scanning transmission electron microscope (STEM) images and energy-dispersive X-ray spectroscopy (EDX) analyses, it was evident that the Nb atoms diffused into the bottom electrode of the Nb/Al/AlOx/Nb junction, while a smaller number diffused into the bottom electrode of the Nb/Al/AlOx/Al/Nb junction. Therefore, we conclude that the extra Al layer effectively acted as a buffer layer that prevented the Nb atoms from diffusing into the insulator and bottom electrode. The presence of the top Al layer is expected to favorably improve the quality of junctions with a very high current density, and support the extension of the RF and IF bandwidths of SIS mixers.

This paper introduces and uses spider monkey optimization (SMO) for synthesis sparse linear arrays, which are composed of a uniformly spaced core subarray and an extended sparse subarray. The amplitudes of all the elements and the locations of elements in the extended sparse subarray are optimized by the SMO algorithm to reduce the side lobe levels of the whole array, under a set of practical constraints. To show the efficiency of SMO, different examples are presented and solved. Simulation results of the sparse arrays designed by SMO are compared with published results to verify the effectiveness of the SMO method.

Given an undirected graph G, an edge dominating set is a subset F of edges such that each edge not in F is adjacent to some edge in F, and computing the minimum size of an edge dominating set is known to be NP-hard. Since the size of any edge dominating set is at least half of the maximum size µ(G) of a matching in G, we study the problem of testing whether a given graph G has an edge dominating set of size ⌈µ(G)/2⌉ or not. In this paper, we prove that the problem is NP-complete, whereas we design an O*(2.0801µ(G)/2)-time and polynomial-space algorithm to the problem.

In this paper we study a recently proposed variant of the facility location problem, called the r-gathering problem. Given an integer r, a set C of customers, a set F of facilities, and a connecting cost co(c, f) for each pair of c ∈ C and f ∈ F, an r-gathering of customers C to facilities F is an assignment A of C to open facilities F' ⊆ F such that at least r customers are assigned to each open facility. We give an algorithm to find an r-gathering with the minimum cost, where the cost is maxc ∈ C{co(c, A(c))}, when all C and F are on the real line.

A ladder lottery, known as “Amidakuji” in Japan, is one of the most popular lotteries. In this paper, we consider the problems of enumeration, counting, and random generation of the ladder lotteries. For given two positive integers n and b, we give algorithms of enumeration, counting, and random generation of ladder lotteries with n lines and b bars. The running time of the enumeration algorithm is O(n + b) time for each. The running time of the counting algorithm is O(nb3) time. The random generation algorithm takes O(nb3) time for preprocess, and then it generates a ladder lottery in O(n + b) for each uniformly at random.

This paper proposes secure regenerating codes that are composed of non-secure regenerating codes and a new all-or-nothing transform. Unlike the previous analysis of secure regenerating codes, the security of the proposed codes is analyzed in the sense of the indistinguishability. The advantage of the proposed codes is that the overhead caused by the security against eavesdropping is much less than that of previous secure regenerating codes. The security of the proposed codes against eavesdropping mainly depends on the new all-or-nothing transform.

Narrow swipe sensor based systems have drawn more and more attention in recent years. However, the size of captured image is significantly smaller than that obtained from the traditional area fingerprint sensor. Under this condition the available minutiae number is also limited. Therefore, only employing minutiae with the standard associated feature can hardly achieve high verification accuracy. To solve this problem, we present a novel Hybrid Minutiae Descriptor (HMD) which consists of two modules. The first one: Minutiae Ridge-Valley Orientation Descriptor captures the orientation information around minutia and also the trace points located at associated ridge and valley. The second one: Gabor Binary Code extracts and codes the image patch around minutiae. The proposed HMD enhances the representation capability of minutiae feature, and can be matched very efficiently. Experiments conducted over public databases and the database captured by the narrow swipe sensor show that this innovative method gives rise to significant improvements in reducing FRR (False Reject Rate) and EER (Equal Error Rate).

An 8-issue superscalar core generally requires a 24-port RAM for the register file. The area and energy consumption of a multiported RAM increase in proportional to the square of the number of ports. A register cache can reduce the area and energy consumption of the register file. However, earlier register cache systems suffer from lower IPC caused by register cache misses. Thus, we proposed the Non-Latency-Oriented Register Cache System (NORCS) to solve the IPC problem with a modified pipeline. We evaluated NORCS mainly from the viewpoint of microarchitecture in the original article, and showed that NORCS maintains almost the same IPC as conventional register files. Researchers in NVIDIA adopted the same idea for their GPUs. However, the evaluation was not sufficient from the viewpoint of LSI design. In the original article, we used CACTI to evaluate the area and energy consumption. CACTI is a design space exploration tool for cache design, and adopts some rough approximations. Therefore, this paper shows design of NORCS with FreePDK45, an open source process design kit for 45nm technology. We performed manual layout of the memory cells and arrays of NORCS, and executed SPICE simulation with RC parasitics extracted from the layout. The results show that, from a full-port register file, an 8-entry NORCS achieves a 75.2% and 48.2% reduction in area and energy consumption, respectively. The results also include the latency which we did not present in our original article. The latencies of critical path is 307ps and 318ps for an 8-entry NORCS and a conventional multiported register file, respectively, when the same two cycles are allocated to register file read.

This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.

An equivalent-circuit model is an effective tool for the analysis and design of metamaterials. This paper describes a systematic and theoretical method for the circuit modeling of meta-atoms. We focus on the structures of wired metallic spheres and propose a method for deriving a sophisticated equivalent circuit that has the same topology as the wires using the partial element equivalent circuit (PEEC) method. Our model contains the effect of external electromagnetic coupling: excitation by an external field modeled by voltage sources and radiation modeled by the radiation resistances for each mode. The equivalent-circuit model provides the characteristics of meta-atoms such as the resonant frequencies and the resonant modes induced by the current distribution in the wires by an external excitation. Although the model is obtained by a very coarse discretization, it provides a good agreement with an electromagnetic simulation.