Effective indoor localization is the essential part of VR (Virtual Reality) and AR (Augmented Reality) technologies. Tracking the RGB-D camera becomes more popular since it can capture the relatively accurate color and depth information at the same time. With the recovered colorful point cloud, the traditional ICP (Iterative Closest Point) algorithm can be used to estimate the camera poses and reconstruct the scene. However, many works focus on improving ICP for processing the general scene and ignore the practical significance of effective initialization under the specific conditions, such as the indoor scene for VR or AR. In this work, a novel indoor prior based initialization method has been proposed to estimate the initial motion for ICP algorithm. We introduce the generation process of colorful point cloud at first, and then introduce the camera rotation initialization method for ICP in detail. A fast region growing based method is used to detect planes in an indoor frame. After we merge those small planes and pick up the two biggest unparallel ones in each frame, a novel rotation estimation method can be employed for the adjacent frames. We evaluate the effectiveness of our method by means of qualitative observation of reconstruction result because of the lack of the ground truth. Experimental results show that our method can not only fix the failure cases, but also can reduce the ICP iteration steps significantly.

The purpose of this study was to examine an efficient interval encoding method with a slow-frame-rate image sensor, and show that the encoding can work to capture heart rates from multiple persons. Visible light communication (VLC) with an image sensor is a powerful method for obtaining data from sensors distributed in the field with their positional information. However, the capturing speed of the camera is usually not fast enough to transfer interval information like the heart rate. To overcome this problem, we have developed an event timing (ET) encoding method. In ET encoding, sensor units detect the occurrence of heart beat event and send their timing through a sequence of flashing lights. The first flash signal provides the rough timing and subsequent signals give the precise timing. Our theoretical analysis shows that in most cases the ET encoding method performs better than simple encoding methods. Heart rate transfer from multiple persons was examined as an example of the method's capabilities. In the experimental setup, the developed system successfully monitored heart rates from several participants.

This paper proposes a formal approach of verifying ubiquitous computing application scenarios. Ubiquitous computing application scenarios assume that there are a lot of devices and physical things with computation and communication capabilities, which are called smart objects, and these are interacted with each other. Each of these interactions among smart objects is called “federation”, and these federations form a ubiquitous computing application scenario. Previously, Yuzuru Tanaka proposed “a proximity-based federation model among smart objects”, which is intended for liberating ubiquitous computing from stereotyped application scenarios. However, there are still challenges to establish the verification method of this model. This paper proposes a verification method of this model through model checking. Model checking is one of the most popular formal verification approach and it is often used in various fields of industry. Model checking is conducted using a Kripke structure which is a formal state transition model. We introduce a context catalytic reaction network (CCRN) to handle this federation model as a formal state transition model. We also give an algorithm to transform a CCRN into a Kripke structure and we conduct a case study of ubiquitous computing scenario verification, using this algorithm and the model checking. Finally, we discuss the advantages of our formal approach by showing the difficulties of our target problem experimentally.

A power packet dispatching system is proposed to realize the function of power on demand. This system distributes electrical power in quantized form, which is called power processing. This system has extensibility and flexibility. Here, we propose to use the power packet dispatching system as the next generation power distribution system in self-established and closed system such as robots, cars, and aircrafts. This paper introduces the concept and the required researches to take the power packet dispatching system in practical phase from the total viewpoints of devices, circuits, power electronics, system control, computer network, and bio-inspired power consumption.

Locally repairable codes (LRCs) have attracted much interest recently due to their applications in distributed storage systems. In an [n,k,d] linear code, a code symbol is said to have locality r if it can be repaired by accessing at most r other code symbols. An (n,k,r) LRC with locality r for the information symbols has minimum distance d≤n-k-⌈k/r⌉+2. In this letter, we study single-parity LRCs where every repair group contains exactly one parity symbol. Firstly, we give a new characterization of single-parity LRCs based on the standard form of generator matrices. For the optimal single-parity LRCs meeting the Singleton-like bound, we give necessary conditions on the structures of generator matrices. Then we construct all the optimal binary single-parity LRCs meeting the Singleton-like bound d≤n-k-⌈k/r⌉+2.

The software development process is front-loaded when formal specification is deployed and as a consequence more problems are identified and solved at an earlier point of time. This places extra importance on the quality and efficiency of the different formal specification tasks. We use the term “exploratory modeling” to denote the modeling that is conducted during the early stages of software development before the requirements are clearly understood. We believe tools that support not only rigorous but also flexible construction of the specification at the same time are helpful in such exploratory modeling phases. This paper presents a web-based IDE named VDMPad to demonstrate the concept of exploratory modeling. VDMPad has been evaluated by experienced professional VDM engineers from industry. The positive evaluation resulting from such industrial users are presented. It is believed that flexible and rigorous tools for exploratory modeling will help to improve the productivity of the industrial software developments by making the formal specification phase more efficient.

In the newly finalized video coding standard, namely high efficiency video coding (HEVC), new notations like coding unit (CU), prediction unit (PU) and transformation unit (TU) are introduced to improve the coding performance. As a result, the reconstruction loop in intra encoding is heavily burdened to choose the best partitions or modes for them. In order to solve the bottleneck problems in cycle and hardware cost, this paper proposed a high-throughput and compact implementation for such a reconstruction loop. By “high-throughput”, it refers to that it has a fixed throughput of 32 pixel/cycle independent of the TU/PU size (except for 4×4 TUs). By “compact”, it refers to that it fully explores the reusability between discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) as well as that between quantization (Q) and de-quantization (IQ). Besides the contributions made in designing related hardware, this paper also provides a universal formula to analyze the cycle cost of the reconstruction loop and proposed a parallel-process scheme to further reduce the cycle cost. This design is verified on the Stratix IV FPGA. The basic structure achieved a maximum frequency of 150MHz and a hardware cost of 64K ALUTs, which could support the real time TU/PU partition decision for 4K×2K@20fps videos.

Spatial modulation (SM) is introduced into layered space-time coding (L-STC) used in image sensor (IS)-based visible light communication (VLC) systems. STC was basically investigated for extending the communication range of the IS-based VLC link [10], although it is out of the range when IS receivers are at the long distance from the LED array of the transmitter where the number of pixels capturing the transmitter on the image plane is less than the number of LEDs of the array. Furthermore, L-STC was done in [11] for increasing the reception rate with improving the pixel resolution while the receiver was approaching the transmitter. In this paper, SM is combined into L-STC by mapping additional information bits on the location of the pair of STC bit matrices of each layer. Experimental results show that additional SM bits are extracted with no error, without deteriorating the reception quality of and shrinking the transmission range of the original L-STC.

We investigate a finite-sized self-complementary bow-tie antenna (SC-BTA) integrated with a semiconductor mesa with respect to radiation characteristics such as the peak radiation frequency and bandwidth around the fundamental radiation mode. For this investigation, we utilize an equivalent circuit model of the SC-BTA derived in our previous work and a finite element method solver. Moreover, we derive design guidelines for the radiation characteristics in the form of size scaling-rules with respect to the antenna outer size for a terahertz transmitter.

Image sensor communication (ISC), a type of visible light communication, is an emerging wireless communication technology that uses LEDs to transmit a signal and uses an image sensor in a camera to receive the signal. This paper discusses the present status of and future trends in ISC by describing the essential characteristics and features of ISC. Moreover, we overview the products and expected future applications of ISC.

High-resolution bio-imaging is a key component for the advancement of life science. CMOS electronics is one of the promising candidates for emerging high-resolution devices because it offers nano-scale transistors. However, the resolution of the existing CMOS bio-imaging devices is several micrometers, which is insufficient for analyzing small objects such as bacteria and viruses. This paper presents the results of an analysis of the scalability of a current-mode analog-to-time converter (CMATC) to develop a high-resolution CMOS biosensor array. Simulations were performed using 0.6-µm, 0.25-µm, and 0.065-µm CMOS technology nodes. The Simulation results for the power consumption and resolution (cell size) showed that the CMATC has high-scalability and is a promising candidate to enable high-resolution CMOS bio-imaging.

In general, semi-supervised clustering can outperform unsupervised clustering. Since 2001, pairwise constraints for semi-supervised clustering have been an important paradigm in this field. In this paper, we show that pairwise constraints (ECs) can affect the performance of clustering in certain situations and analyze the reasons for this in detail. To overcome these disadvantages, we first outline some exemplars constraints. Based on these constraints, we then describe a semi-supervised clustering framework, and design an exemplars constraints expectation-maximization algorithm. Finally, standard datasets are selected for experiments, and experimental results are presented, which show that the exemplars constraints outperform the corresponding unsupervised clustering and semi-supervised algorithms based on pairwise constraints.

We evaluated a technique for protecting the copyright of digital data for 3-D printing. To embed copyright information, the inside of a 3-D printed object is constructed from fine domains that have different physical characteristics from those of the object's main body surrounding them, and to read out the embedded information, these fine domains inside the objects are detected using nondestructive inspections such as X-ray photography or thermography. In the evaluation, copyright information embedded inside the 3-D printed object was expressed using the depth of fine cavities inside the object, and X-ray photography were used for reading them out from the object. The test sample was a cuboid 46mm wide, 42mm long, and 20mm deep. The cavities were 2mm wide and 2mm long. The difference in the depths of the cavities appeared as a difference in the luminance in the X-ray photographs, and 21 levels of depth could be detected on the basis of the difference in luminance. These results indicate that under the conditions of the experiment, each cavity expressed 4 to 5bits of information with its depth. We demonstrated that the proposed technique had the possibility of embedding a sufficient volume of information for expressing copyright information by using the depths of cavities.

Subspace representation model is an important subset of visual tracking algorithms. Compared with models performed on the original data space, subspace representation model can effectively reduce the computational complexity, and filter out high dimensional noises. However, for some complicated situations, e.g., dramatic illumination changing, large area of occlusion and abrupt object drifting, traditional subspace representation models may fail to handle the visual tracking task. In this paper, we propose a novel subspace representation algorithm for robust visual tracking by using low-rank representation with graph constraints (LRGC). Low-rank representation has been well-known for its superiority of handling corrupted samples, and graph constraint is flexible to characterize sample relationship. In this paper, we aim to exploit benefits from both low-rank representation and graph constraint, and deploy it to handle challenging visual tracking problems. Specifically, we first propose a novel graph structure to characterize the relationship of target object in different observation states. Then we learn a subspace by jointly optimizing low-rank representation and graph embedding in a unified framework. Finally, the learned subspace is embedded into a Bayesian inference framework by using the dynamical model and the observation model. Experiments on several video benchmarks demonstrate that our algorithm performs better than traditional ones, especially in dynamically changing and drifting situations.

In this paper, we propose an algorithm that enhances the number of pixels for high-speed imaging. High-speed cameras have a principle problem that the number of pixels reduces when the number of frames per second (fps) increases. To enhance the number of pixels, we suppose an optical structure that block-randomly selects some percent of pixels in an image. Then, we need to reconstruct the entire image. For this, a state-of-the-art method takes three-dimensional reconstruction strategy, which requires a heavy computational cost in terms of time. To reduce the cost, the proposed method reconstructs the entire image frame-by-frame using a new cost function exploiting two types of sparsity. One is within each frame and the other is induced from the similarity between adjacent frames. The latter further means not only in the image domain, but also in a sparsifying transformed domain. Since the cost function we define is convex, we can find the optimal solution using a convex optimization technique with small computational cost. We conducted simulations using grayscale image sequences. The results show that the proposed method produces a sequence, mostly the same quality as the state-of-the-art method, with dramatically less computational time.

Particle filter algorithm is an important algorithm in the field of target tracking. however, this algorithm faces the problem of sample impoverishment which is caused by the introduction of re-sampling and easily affected by illumination variation. This problem seriously affects the tracking performance of a particle filter algorithm. To solve this problem, we introduce a particle filter target tracking algorithm based on a dynamic niche genetic algorithm. The application of this dynamic niche genetic algorithm to re-sampling ensures particle diversity and dynamically fuses the color and profile features of the target in order to increase the algorithm accuracy under the illumination variation. According to the test results, the proposed algorithm accurately tracks the target, significantly increases the number of particles, enhances the particle diversity, and exhibits better robustness and better accuracy.

The massive multiple input multiple output (MIMO) system with large-scale antenna array at base station (BS) simultaneously communicates with many mobile stations (MSs) ensuring high reliability using the pre-coding. But, in mobile communication, the performance of the pre-coding is degraded by fast fading. For improving the performance of the pre-coding, this letter proposes the power control scheme of the new approach that has the variable step size using the statistical characteristic of fast fading and Doppler frequency. From the simulation results, it is shown that the proposed scheme improves signal-to-interference-plus-noise ratio (SINR) performance.

This paper presents a high resolution mixed-domain Delta-Sigma (ΔΣ) time-to-digital converter (TDC) which utilizes a charge pump as time-to-voltage converter, a low resolution SAR ADC as quantizer, and a pair of delay-line digital-to-time converters to form a negative feedback. By never resetting the sampling capacitor of the charge-pump, an integrator is realized and first order noise shaping can be achieved. However, since the integrating capacitor is never cleared, this circuit is prone to charge-sharing issue during input sampling which can degrade TDC's performance. To deal with this issue, a compensation circuit consists of another pair of sampling capacitors and charge-pumps with doubled current is proposed. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 2.5 MHz bandwidth, simulation shows that this TDC achieves 66.4 dB SNDR and 295 fsrms integrated noise for ±1 ns input range. The proposed TDC consumes 1.78 mW power that translates to FoM of 208 fJ/conv.

In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um2 silicon area and consumes 0.18 mW at 1 GS/s.