This letter considers a multiple-channel cognitive radio network (CRN) which can simultaneously sense multiple narrowband channels at a time. Taking the maximization of the CRN's overall throughput as the design objective, the optimization problem of jointly designing sensing time, sensing thresholds and transmission power allocation is formulated under the total power constraint of the CRN and the average interference constraint of the primary network. An iterative algorithm is proposed to obtain the locally optimal values for these parameters. Finally, numerical results show that significant overall throughput gain is achieved through the joint design.

We consider secure wireless communications, where a source is communicating to a destination in the presence of K (K > 1) eavesdroppers. The source and destination both are equipped with multiple antennas, while each eavesdropper has a single antenna. The source aims to maximize the communication rate to the destination, while concealing the message from all the eavesdroppers. Combined with selective diversity, we propose a heuristic secrecy transmission scheme where the multiple-input-multiple-output (MIMO) secrecy channel is simplified into a multiple-input-single-output (MISO) one with the highest orthogonality to the eavesdropper channels. Then convex optimization is applied to obtain the optimal transmit covariance matrix for this selected MISO secrecy channel. Numerical results are provided to illustrate the efficacy of the proposed scheme.

This letter proposes an adaptive scheme that switches between cooperative and non-cooperative transmission for multicell downlink systems in Kronecker spatially correlated channels, which exploits statistical channel state information (CSI). Based on the received signal-to-noise ratios (SNRs) and a cooperation metric, we propose a simple base station (BS) association method and then derive low-SNR capacity approximations for both cooperative and non-cooperative systems. Using the results, we provide a low-complexity efficient cooperation switching method to enhance the system capacity. Results show that the proposed method is more efficient than the conventional method to search the switching point.

This paper proposes a utility function-based scheduling algorithm for integrated real-time and non-real-time services in long-term evolution systems. The proposed utility function satisfies the target dropping ratio of real-time users; it uses the delay constraint and increases the throughput of non-real-time users by scheduling real-time users together with non-real-time users. Simulation results show that the proposed scheduling algorithm significantly improves the throughput of non-real-time users without sacrificing the quality of service of real-time users.

We introduce the distributed estimation of a random vector signal in wireless sensor networks that follow coherent multiple access channel model. We adopt the linear minimum mean squared error fusion rule. The problem of interest is to design linear coding matrices for those sensors in the network so as to minimize mean squared error of the estimated vector signal under a total power constraint. We show that the problem can be formulated as a convex optimization problem and we obtain closed form expressions of the coding matrices. Numerical results are used to illustrate the performance of the proposed method.

In this paper, a sepic-type single-stage electronic ballast (STSSEB) is proposed, which is derived from the combination of a sepic converter and a half-bridge inverter. The ballast can not only step down input voltage directly but achieve high power factor, reduce voltage stress, improve efficiency and lower cost. Since component stress is reduced significantly, the presented ballast can be applied to high voltage mains. Derivation of the STSSEB is first presented. Then, analysis, design and practical consideration for the STSSEB are discussed. A 347 Vac 60 W prototype has been simulated and implemented. Simulations and experimental results have verified the feasibility of the proposed STSSEB.

This paper examines the robust performance of a load torque observer for the position control of a surface-mounted permanent magnet synchronous motor (PMSM) under parameter uncertainties. The load torque observer has been widely employed to compensate for unknown slow-varying disturbances without explicit analysis on the robustness against parameter uncertainties. By using the singular perturbation theory this paper presents an analysis on the robust performance of the load torque observer based on the reduced-order estimator. As the observer poles are placed sufficiently left of the complex plane, the feedforward compensation with estimation can recover nominal system performance without parameter uncertainties and load torque disturbance. An example shows the performance of the load torque observer.

In deep-submicron era, wire delay is becoming a bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). Though DRFM-IID is also one of the DR-based architectures, it is considered more practical than the previously proposed DRFM, in terms of delay model. With such delay consideration, the synthesis task is inherently more complicated than the one without inter-island delay concern since uncertain interconnect latency is very likely to seriously impact on the whole system performance. Therefore we also develop a performance-driven architectural synthesis framework targeting DRFM-IID. Several factors for evaluating the quality of results, such as number of inter-island transfers, timing-criticality of transfer, and resource utilization balancing, are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication.

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

Cooperative diversity using space-time codes offers effective space diversity with low complexity, but the scheme needs the space-time coding process in the relay nodes. We propose a simple cooperative relay scheme that uses space-time coding. In the scheme, the source node transmits the Alamouti coded signal sequences and the sink node receives the signal sequence via the two coordinated relay nodes. At the relay nodes, the operation procedure is just permutation and forwarding of the signal sequence. In the proposed scheme, none of the relay nodes need quadrature detection and space-time coding and the simple relay process offers effective space diversity. Moreover, simulations show the effectiveness of the proposed relay process by some simulations.

A new near-field source localization algorithm based on a uniform linear array was proposed. The proposed algorithm estimates each parameter separately but does not need pairing parameters. It can be divided into two important steps. The first step is bearing-related electric angle estimation based on the ESPRIT algorithm by constructing a special cumulant matrix. The second step is the other electric angle estimation based on the 1-D MUSIC spectrum. It offers much lower computational complexity than the traditional near-field 2-D MUSIC algorithm and has better performance than the high-order ESPRIT algorithm. Simulation results demonstrate that the performance of the proposed algorithm is close to the Cramer-Rao Bound (CRB).

This paper presents an ultra-wideband (UWB) bandpass filter (BPF) with sharp attenuation slope characteristics. The circuit structure consists of an inter-digital finger resonator, parallel-coupled lines and phase matching line. The design of the bandwidth was described by using the even and odd mode characteristic impedances in the resonator structure. The parallel-coupled lines were also designed in the same manner. The parameters of the resonator and two parallel-coupled lines in combination as the BPF were then optimized by the simulation with HFSS. The designed BPF was experimentally fabricated and its measured performances showed the bandwidth from 3.6 to 10 GHz with the 20 dB outband rejection. For the U.S. UWB band design, the matching line was inserted between the two parallel-coupled lines. The matching at both band edges was then qualitatively analyzed on the smithchart. The HFSS simulation results of the structure realized the bandwidth from 3.1 to 10.6 GHz with sharp attenuation slope characteristics for SWR < 2.0. The measurement results agree well with the simulation results.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

We demonstrate the wavelength trimming of MEMS VCSELs by etching a cantilever-shaped top mirror using FIB etching. The proposed technique can be used for the post-process precise wavelength allocation of athermal MEMS VCSELs. The modeling and experimental results on 850 nm MEMS VCSELs are presented. The results show a possibility of realizing both red-shift and blue-shift wavelength changes by choosing the etching area of the cantilever.

This letter proposes a practical algorithm for video transmission of the scalable extension of H.264/AVC (SVC) over limited bit-rate and varying channel signal-to-noise ratio (SNR). The proposal consists of SVC source-layer dropping and layered FEC using LDPC codes to maximize the video quality. The experimental results show that the proposed method realizes better video quality than the compared unequal error protection (UEP) without source-layer dropping. This implies that the dropping of a certain number of source-layers and using the resultant bit-budget for channel coding is more effective than the other UEP case which uses all possible source-layers.

In this paper, we introduce a generalized minimum mean-square error short-time spectral amplitude estimator with a new prior estimation of the speech probability density function based on moment-cumulant transformation. From the objective and subjective evaluation experiments, we show the improved noise reduction performance of the proposed method.

Substrate noise coupling has been seriously concerned in the design of advanced analog and radio frequency (RF) integrated circuits (ICs). This paper reviews recent advancements in the modeling, analysis, and evaluation of substrate noise coupling at IC chip level. Noise generation from digital circuits and propagation to the area of analog circuits are clearly visualized both by full-chip simulation as well as by on-chip measurements, for silicon test vehicles. The impacts of substrate noise coupling are also in-depth discussed at device, circuit, as well as system levels. Overall understanding of substrate noise coupling will then provide the basics for highly reliable design of analog and RF ICs.

We investigated optical transmission characteristics of aluminum thin films with periodic hole arrays in sub-wavelength. We divided white light into several color spectra using a color filter based on the surface plasmon resonance (SPR) utilizing aluminum showing high plasma frequency. By optimizing a hole-array period, hole shape, polarization and index difference of two surface, transmittance of 30% and full-width at half-maximum of around 100 nm were achieved.

In this paper, we propose two new falsification attacks against Wi-Fi Protected Access Temporal Key Integrity Protocol (WPA-TKIP). A previous realistic attack succeeds only for a network that supports IEEE 802.11e QoS features by both an access point (AP) and a client, and it has an execution time of 12–15 min, in which it recovers a message integrity code (MIC) key from an ARP packet. Our first attack reduces the execution time for recovering a MIC key. It can recover the MIC key within 7–8 min. Our second attack expands its targets that can be attacked. This attack focuses on a new vulnerability of QoS packet processing, and this vulnerability can remove the condition that the AP supports IEEE 802.11e. In addition, we discovered another vulnerability by which our attack succeeds under the condition that the chipset of the client supports IEEE 802.11e even if the client disables this standard through the OS. We demonstrate that chipsets developed by several kinds of vendors have the same vulnerability.

The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.