The Viterbi algorithm is widely used for decoding of the convolutional codes. The trace-back method is preferable to the register exchange method because of lower power consumption especially for convolutional codes with many states. A drawback of the conventional trace-back is that it generally requires long latency to obtain the decoded data. In this paper, a method of the trace-back with source states instead of decision bits is proposed which reduces the number of memory accesses. The dedicated memory is also presented which supports the proposed trace-back method. The reduced memory accesses result in smaller power consumption and a shorer decode latency than the conventional method.

Maximum likelihood block signal detection employing QR decomposition and M-algorithm (QRM-MLBD) can significantly improve the bit error rate (BER) performance of single-carrier (SC) transmission while significantly reducing the computational complexity compared to maximum likelihood detection (MLD). However, its computational complexity is still high. In this paper, we propose the computationally efficient 2-step QRM-MLBD. Compared to conventional QRM-MLBD, the number of symbol candidates can be reduced by using preliminary decision made by minimum mean square error based frequency-domain equalization (MMSE-FDE). The BER performance achievable by 2-step QRM-MLBD is evaluated by computer simulation. It is shown that it can significantly reduce the computational complexity while achieving almost the same BER performance as the conventional QRM-MLBD.

Hypercomplex polar Fourier analysis treats a signal as a vector field and generalizes the conventional polar Fourier analysis. It can handle signals represented by hypercomplex numbers such as color images. Hypercomplex polar Fourier analysis is reversible that means it can reconstruct image. Its coefficient has rotation invariance property that can be used for feature extraction. However in order to increase the computation speed, fast algorithm is needed especially for image processing applications like realtime systems and limited resource platforms. This paper presents fast hypercomplex polar Fourier analysis based on symmetric properties and mathematical properties of trigonometric functions. Proposed fast hypercomplex polar Fourier analysis computes symmetric points simultaneously, which significantly reduce the computation time.

This paper proposes a direction-of-arrival (DOA) estimation method of multiple speech sources from a stereophonic mixture in an underdetermined case where the number of sources exceeds the number of sensors. The method relies on the sparseness of speech signals in time-frequency (T-F) domain representation which means multiple independent speakers have a small overlap. At first, a selection of T-F cells bearing reliable spatial information is proposed by an introduced reliability index which is defined by the estimated interaural phase difference at each T-F cell. Then, a statistical error propagation model between the phase difference at T-F cell and its consequent DOA is introduced. By employing this model and the sparseness in T-F domain the DOA estimation problem is altered to obtaining local peaks of probability density function of DOA. Finally the kernel density estimator approach based on the proposed statistical model is applied. The performance of the proposed method is assessed by conducted experiments. Our method outperforms others both in accuracy for real observed data and in robustness for simulation with additional diffused noise.

Zero-knowledge arguments allows one party to prove that a statement is true, without leaking any other information than the truth of the statement. In many applications such as verifiable shuffle (as a practical application) and circuit satisfiability (as a theoretical application), zero-knowledge arguments for mathematical statements related to linear algebra are essentially used. Groth proposed (at CRYPTO 2009) an elegant methodology for zero-knowledge arguments for linear algebraic relations over finite fields. He obtained zero-knowledge arguments of the sub-linear size for linear algebra using reductions from linear algebraic relations to equations of the form z=x*'y, where x, y ∈ Fnp are committed vectors, z ∈ Fp is a committed element, and *': FnpFnpFp is a bilinear map. These reductions impose additional rounds on zero-knowledge arguments of the sub-linear size. The round complexity of interactive zero-knowledge arguments is an important measure along with communication and computational complexities. We focus on minimizing the round complexity of sub-linear zero-knowledge arguments for linear algebra. To reduce round complexity, we propose a general transformation from a t-round zero-knowledge argument, satisfying mild conditions, to a (t-2)-round zero-knowledge argument; this transformation is of independent interest.

This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9 bit, 580 fs resolution in a 0.18 µm CMOS technology with 0.04 mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5 MS/s ranges from 10.8 to 12.6 mW depending on the input time intervals.

Keith Salvin presented a key exchange protocol using matrices in the general linear group, GL(r,Zn), where n is the product of two distinct large primes. The system is fully specified in the US patent number 7346162 issued in 2008. In the patent claims, it is argued that the best way to break this system is to factor n. Furthermore, for efficiency reasons, it is suggested to use r=2. In this letter, we show that this cryptosystem can be easily broken by solving a set of consistent homogeneous r2 linear equations in 2r unknowns over Zn.

The development of ontology at the instance level requires the extraction of the terms defining the instances from various data sources. These instances then are linked to the concepts of the ontology, and relationships are created between these instances for the next step. However, before establishing links among data, ontology engineers must classify terms or instances from a web document into an ontology concept. The tool for help ontology engineer in this task is called ontology population. The present research is not suitable for ontology development applications, such as long time processing or analyzing large or noisy data sets. OntoPop system introduces a methodology to solve these problems, which comprises two parts. First, we select meaningful features from syntactic relations, which can produce more significant features than any other method. Second, we differentiate feature meaning and reduce noise based on latent semantic analysis. Experimental evaluation demonstrates that the OntoPop works well, significantly out-performing the accuracy of 49.64%, a learning accuracy of 76.93%, and executes time of 5.46 second/instance.

Along with the miniaturization of CMOS-LSIs, control methods for LSIs have been extensively developed. The most predominant method is to digitize observed values as early as possible and to use digital control. Thus, many types of analog-to-digital converters (ADCs) have been developed such as temperature, time, delay, and frequency converters. ADCs are the easiest circuits into which digital correction methods can be introduced because their outputs are digital. Various types of calibration method have been developed, which has markedly improved the figure of merits by alleviating margins for device variations. The above calibration and correction methods not only overcome a circuit's weak points but also give us the chance to develop quite new circuit topologies and systems. In this paper, several digital calibration and correction methods for major analog-to-digital converters are described, such as pipelined ADCs, delta-sigma ADCs, and successive approximation ADCs.

In this paper, performance analysis of a cognitive radio network is conducted. In the network, there is imperfect sensing and the wireless channel is a Gilbert-Elliott channel. The focus is on the network's capacity in serving traffic with delay constraints. Specifically, the maximum traffic arrival rates of both primary users and secondary users, which the network can support with guaranteed delay bounds, are investigated. The analysis is based on stochastic network calculus. A general relationship between delay bounds, traffic patterns and important characteristics such as spectrum sensing errors and channel fading of the cognitive radio network is derived. This relationship lays a foundation for finding the capacity under different traffic scenarios. Two specific traffic types are exemplified, namely periodic traffic and Poisson traffic. Analytical results are presented in comparison with simulation results. The comparison shows a good match between them, validating the analysis.

Cognitive radio is an emerging technology to further improve the efficiency of spectrum use. Due to the nature of the technology, it has many facets, including its enabling technologies, its implementation issues and its regulatory implications. In ITU-R (International Telecommunications Union – Radiocommunication sector), cognitive radio systems are currently being studied so that ITU-R can have a clear picture on this new technology and its potential regulatory implications, from a viewpoint of global spectrum management. This paper introduces the recent results of the ITU-R studies on cognitive radio on both regulatory and technical aspects. This paper represents a personal opinion of the author, but not an official view of the ITU-R.

In this paper, we study the problem of distributed spectrum allocation under a vertical spectrum sharing scenario in a cognitive radio network. The secondary users share the spectrum licensed to the primary user by observing the activity statistics of the primary users, and regulate their transmission strategy in order to abide by the spectrum sharing etiquette. When the primary user is inactive in a subset of the available frequency bands, from the perspective of the secondary users the problem reduces to a distributed horizontal spectrum sharing. For a specific class of networks, the latter problem is addressed by the recently proposed GADIA algorithm [1]. In this paper, we present analytical and numerical results on the performance of the GADIA algorithm in conjunction with the above-mentioned vertical spectrum sharing scenario. These results reveal near-optimal performance guarantees for the overall vertical spectrum sharing scenario.

A method of identifying JPEG 2000 images with different coding parameters, such as code-block sizes, quantization-step sizes, and resolution levels, is presented. It does not produce false-negative matches regardless of different coding parameters (compression rate, code-block size, and discrete wavelet transform (DWT) resolutions levels) or quantization step sizes. This feature is not provided by conventional methods. Moreover, the proposed approach is fast because it uses the number of zero-bit-planes that can be extracted from the JPEG 2000 codestream by only parsing the header information without embedded block coding with optimized truncation (EBCOT) decoding. The experimental results revealed the effectiveness of image identification based on the new method.

This paper presents design of a novel high speed booth encoder-decoder in a 0.35 µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.

We present an economical and fault-tolerant load balancing strategy (EFTLBS) based on an operator replication mechanism and a load shedding method, that fully utilizes the network resources to realize continuous and highly-available data stream processing without dynamic operator migration over wide area networks. In this paper, we first design an economical operator distribution (EOD) plan based on a bin-packing model under the constraints of each stream bandwidth as well as each server's CPU capacity. Next, we devise super-operator (SO) that load balances multi-degree operator replicas. Moreover, for improving the fault-tolerance of the system, we color the SOs based on a coloring bin-packing (CBP) model that assigns peer operator replicas to different servers. To minimize the effects of input rate bursts upon the system, we take advantage of a load shedding method while keeping the QoS guarantees made by the system based on the SO scheme and the CBP model. Finally, we substantiate the utility of our work through experiments on ns-3.

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closed-loop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/, current consumption of 14 µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 µm CMOS process.

This work studies the benefits of heterogeneous cellular networks with overlapping picocells in a large macrocell. We consider three different strategies for resource allocation and cell association. The first model employs a spectrum overlapping strategy with an SINR-based cell association. The second model avoids the interference between macrocell and picocell through a spectrum splitting strategy. Furthermore, picocell range expansion is also considered in this strategy to enable a load balancing between the macrocell and picocells. The last model is a hybrid one, called as fractional spectrum splitting strategy, where spectrum splitting strategy is only applied at the picocell-edge, while the picocell-inner reuses the spectrum of the macrocell. We constructs resource allocation optimization problem for these strategies to maximize the system rate. Our results show that in terms of system rate, all the three strategies outperform the performance of macrocell-only case, which shows the benefit of heterogeneous networks. Moreover, fractional spectrum splitting strategy provides highest system rate at the expense of outage user rate degradation due to inter-macro-pico interference. Spectrum overlapping model provides the second highest system rate gain and also improves outage user rate owing to full spectrum reuse and the benefit of macro diversity, while spectrum splitting model achieves a moderate system rate gain.

In a large queuing system, the effect of the ratio of the filled data on the queue and waiting time from the head of a queue to the service gate are important factors for process efficiency because they are too large to ignore. However, many research works assumed that the factors can be considered to be negligible according to the queuing theory. Thus, the existing queuing models are not applicable to the design of large-scale systems. Such a system could be used as a product classification center for a home delivery service. In this paper, we propose a tree-queue model for large-scale systems that is more adaptive to efficient processes compared to existing models. We analyze and design a mean waiting time equation related to the ratio of the filled data in the queue. Based on simulations, the proposed model demonstrated improvement in process-efficiency, and it is more suitable to realistic system modeling than other compared models for large-scale systems.

In this letter, we apply dynamic software updating to long-lived applications on the DDS middleware while minimizing service interruption and satisfying Quality of Service (QoS) requirements. We dynamically updated applications which run on a commercial DDS implementation to demonstrate the applicability of our approach to dynamic updating. The results show that our update system does not impose an undue performance overhead–all patches could be injected in less than 350 ms and the maximum CPU usage is less than 17%. In addition, the overhead on application throughput due to dynamic updates ranged from 0 to at most 8% and the deadline QoS of the application was satisfied while updating.

This paper presents a new common-mode stabilization method for a CMOS differential cascode Class-E power amplifier with LC-tank based driver stage. The stabilization method is based on the identification of the poles and zeros of the closed-loop transfer function at a critical node. By adding a series resistor at the common-gate node of the cascode transistor, the right-half-plane poles are moved to the left half plane, improving the common-mode stability. The simulation results show that the new method is an effective way to stabilize the PA.