With more digital home appliances and network devices having OSGi as the software management platform, the power-saving capability of the OSGi platform has become a critical issue. This paper is aimed at improving the power-efficiency of the OSGi platform, i.e. reducing the energy consumption with minimum performance degradation. The key to this study is an efficient power-saving technique which exploits the runtime information already available in a Java virtual machine (JVM), the base software of the OSGi platform, to best determine the timing of performing DVFS (Dynamic Voltage and Frequency Scaling). This, technically, involves a phase detection scheme that identifies the memory phase of the OSGi-enabled device/server in a correct and almost effortless way. The overhead of the power-saving procedure is thus minimized, and the system performance is well maintained. We have implemented and evaluated the proposed power-saving approach on an OSGi server, where the Apache Felix OSGi implementation and the DaCapo benchmarks were applied. The results show that this approach can achieve real power-efficiency for the OSGi platform, in which the power consumption is significantly reduced and the performance remains highly competitive, compared with the other power-saving techniques.

Traditional two-microphone noise reduction algorithms to deal with highly nonstationary directional noises generally use the direction of arrival or phase difference information. The performance of these algorithms deteriorate when diffuse noises coexist with nonstationary directional noises in realistic adverse environments. In this paper, we present a two-channel noise reduction algorithm using a spatial information-based speech estimator and a spatial-information-controlled soft-decision noise estimator to improve the noise reduction performance in realistic non-stationary noisy environments. A target presence probability estimator based on Bayes rules using both phase difference and magnitude squared coherence is proposed for soft-decision of noise estimation, so that they can share complementary advantages when both directional noises and diffuse noises are present. Performances of the proposed two-microphone noise reduction algorithm are evaluated by noise reduction, log-spectral distance (LSD) and word recognition rate (WRR) of a distant-talking ASR system in a real room's noisy environment. Experimental results show that the proposed algorithm achieves better noises suppression without further distorting the desired signal components over the comparative dual-channel noise reduction algorithms.

Electrical performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) based on a silicon germanium (Si1-xGex) layer have been investigated in terms of subthreshold swing (SS), on/off current ratio, on-state current (Ion). Cut-off frequency (fT) and maximum oscillation frequency (fmax) were demonstrated from small-signal parameters such as effective gate resistance (Rg), gate-drain capacitance (Cgd), and transconductance (gm). According to the technology computer-aided design (TCAD) simulation results, the current drivability, fT, and fmax of GAA TFETs based on Si1-xGex layer were higher than those of GAA TFETs based on silicon. The simulated devices had 60 nm channel length and 10 nm channel radius. A GAA TFET with x = 0.4 had maximum Ion of 51.4 µA/µm, maximum fT of 72 GHz, and maximum fmax of 610 GHz. Additionally, improvements of performance at the presented device with PNPN junctions were demonstrated in terms of Ion, SS, fT, and fmax. When the device was designed with x = 0.4 and n+ layer width (Wn) = 6 nm, it shows Ion of 271 µA/µm, fT of 245 GHz, and fmax of 1.49 THz at an operating bias (VGS = VDS = 1.0 V).

In a large queuing system, the effect of the ratio of the filled data on the queue and waiting time from the head of a queue to the service gate are important factors for process efficiency because they are too large to ignore. However, many research works assumed that the factors can be considered to be negligible according to the queuing theory. Thus, the existing queuing models are not applicable to the design of large-scale systems. Such a system could be used as a product classification center for a home delivery service. In this paper, we propose a tree-queue model for large-scale systems that is more adaptive to efficient processes compared to existing models. We analyze and design a mean waiting time equation related to the ratio of the filled data in the queue. Based on simulations, the proposed model demonstrated improvement in process-efficiency, and it is more suitable to realistic system modeling than other compared models for large-scale systems.

In this paper, a theoretical analysis of current-controlled (CC-) MOS current mode logic (MCML) is reported. Furthermore, the circuit performance of the CC-MCML with the auto-detection of threshold voltage (Vth) fluctuation is evaluated. The proposed CC-MCML with the auto-detection of Vth fluctuation automatically suppresses the degradation of circuit performance induced by the Vth fluctuations of the transistors automatically, by detecting these fluctuations. When a Vth fluctuation of ± 0.1 V occurs on the circuit, the cutoff frequency of the circuit is increased from 0 Hz to 3.5 GHz by using the proposed CC-MCML with the auto-detection of Vth fluctuation.

In this letter, we apply dynamic software updating to long-lived applications on the DDS middleware while minimizing service interruption and satisfying Quality of Service (QoS) requirements. We dynamically updated applications which run on a commercial DDS implementation to demonstrate the applicability of our approach to dynamic updating. The results show that our update system does not impose an undue performance overhead–all patches could be injected in less than 350 ms and the maximum CPU usage is less than 17%. In addition, the overhead on application throughput due to dynamic updates ranged from 0 to at most 8% and the deadline QoS of the application was satisfied while updating.

As process technology is scaled down, a typical system on a chip (SoC) becomes denser. In scaled process technology, process variation becomes greater and increasingly affects the SoC circuits. Moreover, the process variation strongly affects network-on-chips (NoCs) that have a synchronous network across the chip. Therefore, its network frequency is degraded. We propose a process-variation-adaptive NoC with a variation-adaptive variable-cycle router (VAVCR). The proposed VAVCR can configure its cycle latency adaptively on a processor core basis, corresponding to the process variation. It can increase the network frequency, which is limited by the process variation in a conventional router. Furthermore, we propose a variable-cycle pipeline adaptive routing (VCPAR) method with VAVCR; the proposed VCPAR can reduce packet latency and has tolerance to network congestion. The total execution time reduction of the proposed VAVCR with VCPAR is 15.7%, on average, for five task graphs.

Non-negative matrix factorization (NMF) is widely used for monaural musical sound source separation because of its efficiency and good performance. However, an additional clustering process is required because the musical sound mixture is separated into more signals than the number of musical tracks during NMF separation. In the conventional method, manual clustering or training-based clustering is performed with an additional learning process. Recently, a clustering algorithm based on the mel-frequency cepstrum coefficient (MFCC) was proposed for unsupervised clustering. However, MFCC clustering supplies limited information for clustering. In this paper, we propose various timbre features for unsupervised clustering and a clustering algorithm with these features. Simulation experiments are carried out using various musical sound mixtures. The results indicate that the proposed method improves clustering performance, as compared to conventional MFCC-based clustering.

We propose a new cognitive radio network architecture using the IP multimedia subsystem (IMS) functionality. We implement the cognitive radio network entities standardized in IEEE 1900.4 on the IMS that exchanges RAN and terminal context information between the networks and the terminals to make optimum and immediate reconfiguration decisions. In our proposed architecture, RAN context information is obtained from cellular networks which are directly connected to the IMS. The presence management functions of the IMS are applied to exchange those information in a “push” manner, which enables immediate notification of changes in wireless environment. We evaluate the performance of the proposed context information exchange method, by comparing with the cases that adequate and immediate RAN context information is not available. The evaluation results show that the proposed framework gives 10–30% superior performance than the conventional cognitive radio networks.

In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation. The proposed method iteratively applies behavioral synthesis and floorplanning to obtain a near optimum circuit in the term of latency under given design constraints. To improve latency, behavioral synthesis and floorplanning are carried out so that the delay of the control circuit is minimized and the addition of delay elements to satisfy timing constraints is minimized. We evaluate the effectiveness of the proposed method in terms of latency, area, and the number of timing violations while synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to the circuit synthesized without the proposed method. Also, the proposed method is effective to reduce the number of timing violations.

This paper proposes optical node architectures for the single-layer optical cross-connect (OXC) and hierarchical OXC (HOXC) that utilize dedicated add/drop switches for originating/terminating traffic at a node. For both single-layer OXC and HOXC, three architectures with different restrictions on add/drop capabilities are presented. The performance of the proposed architectures is compared through numerical experiments. The architectures significantly reduce total switch scale and minimize necessary switch size while attaining colorless, directionless and contentionless capabilities.

We previously proposed a unified wireless system called “Flexible Wireless System”. Comprising of flexible access points and a flexible signal processing unit, it collectively receives a wideband spectrum that includes multiple signals from various wireless systems. In cases of simultaneous multiple signal reception, however, reception performance degrades due to the interference among multiple signals. To address this problem, we propose a new signal separation and reconstruction method for spectrally overlapped signals. The method analyzes spectral information obtained by the short-time Fourier transform to extract amplitude and phase values at each center frequency of overlapped signals at a flexible signal processing unit. Using these values enables signals from received radio wave data to be separated and reconstructed for simultaneous multi-system reception. In this paper, the BER performance of the proposed method is evaluated using computer simulations. Also, the performance of the interference suppression is evaluated by analyzing the probability density distribution of the amplitude of the overlapped interference on a symbol of the received signal. Simulation results confirmed the effectiveness of the proposed method.

In this letter, a novel resource allocation method is proposed for Discrete Fourier Transform Spread Orthogonal Frequency Division Multiple Access (DFT-s-OFDMA) systems in Long Term Evolution (LTE). The proposed method is developed based on a minimal metric loss criterion and performs better than the commonly used Recursive Maximum Expansion (RME) method.

This paper demonstrates a FinFET operational amplifier (opamp), which is suitable to be integrated with digital circuits in a scaled low-standby-power (LSTP) technology and operates at extremely low voltage. The opamp is consisting of an adaptive threshold-voltage (Vt) differential pair and a low-voltage source follower using independent-double-gate- (IDG-) FinFETs. These two components enable the opamp to extend the common-mode voltage range (CMR) below the nominal Vt even if the supply voltage is less than 1.0 V. The opamp was implemented by our FinFET technology co-integrating common-DG- (CDG-) and IDG-FinFETs. More than 40-dB DC gain and 1-MHz gain-bandwidth product in the 500-mV-wide input CMR at the supply voltage of 0.7 V was estimated with SPICE simulation. The fabricated chip successfully demonstrated the 0.7-V operation with the 480-mV-wide CMR, even though the nominal Vt was 400 mV.

A Drude-critical points (D-CP) model for considering metal dispersion is newly incorporated into the frequency-dependent FDTD method using the simple trapezoidal recursive convolution (TRC) technique. Numerical accuracy is investigated through the analysis of pulse propagation in a metal (aluminum) cladding waveguide. The TRC technique with a single convolution integral is found to provide higher accuracy, when compared with the recursive convolution counterpart. The methodology is also extended to the unconditionally stable FDTD based on the locally one-dimensional scheme for efficient frequency-dependent calculations.

In Digital Library (DL) applications, digital book clustering is an important and urgent research task. However, it is difficult to conduct effectively because of the great length of digital books. To do the correct clustering for digital books, a novel method based on probabilistic topic model is proposed. Firstly, we build a topic model named LDAC. The main goal of LDAC topic modeling is to effectively extract topics from digital books. Subsequently, Gibbs sampling is applied for parameter inference. Once the model parameters are learned, each book is assigned to the cluster which maximizes the posterior probability. Experimental results demonstrate that our approach based on LDAC is able to achieve significant improvement as compared to the related methods.

Feature selection (FS) plays an important role in pattern recognition and machine learning. FS is applied to dimensionality reduction and its purpose is to select a subset of the original features of a data set which is rich in the most useful information. Most existing FS methods based on rough set theory focus on dependency function, which is based on lower approximation as for evaluating the goodness of a feature subset. However, by determining only information from a positive region but neglecting a boundary region, most relevant information could be invisible. This paper, the maximal lower approximation (Max-Certainty) – minimal boundary region (Min-Uncertainty) criterion, focuses on feature selection methods based on rough set and mutual information which use different values among the lower approximation information and the information contained in the boundary region. The use of this idea can result in higher predictive accuracy than those obtained using the measure based on the positive region (certainty region) alone. This demonstrates that much valuable information can be extracted by using this idea. Experimental results are illustrated for discrete, continuous, and microarray data and compared with other FS methods in terms of subset size and classification accuracy.

This paper investigates the application of inter-cell interference coordination (ICIC) in heterogeneous networks for the LTE-Advanced downlink where picocells are overlaid onto macrocells. In LTE-Advanced, in order to perform ICIC, almost blank subframes (ABSs) are employed, where only the cell-specific reference signal (CRS) is transmitted to protect the subframes in the picocells from severe interference from the macrocells. Furthermore, multicast/broadcast over single-frequency network (MBSFN) subframes are employed to reduce the interference of the CRS on the data channel, although the control channel still suffers from interference from the CRS. When the cell range expansion (CRE), which offload the UEs from macrocells to picocells, is used to improve the system performance, the influence from the CRS increases. In order to assess the influence, the required CRE bias to improve the data channel is investigated based on a system-level simulation under various conditions such as the number of picocells, the protected subframe ratio, and the user distribution. The simulation results show that the cell-edge user throughput is improved with the CRE bias of more than 8 dB, employing ABSs. Furthermore, simulation results show that one dominant source of interference is observed for the sets of user equipment (UEs) connected to the picocells via CRE with such a bias value. Based on observation, the influence that the CRS has on the control channel, i.e., physical control format indicator channel (PCFICH), and physical downlink control channel (PDCCH) is investigated based on a link-level simulation combined with a system-level simulation. The simulation results show that protecting the PCFICH is very important compared to protecting the PDCCH, since the block error rate (BLER) performance of the PCFICH becomes worse than the required BLER of 10-3 to support various conditions, although the BLER performance of the PDCCH can exceed the required BLER of 10-2 by spanning the PDCCH over three OFDM symbols.

Developing a rapid prototyping environment utilizing hardware description languages (HDLs) and conventional FPGAs can help ease and conquer the difficulties caused by the complexity of asynchronous digital systems and the advance of VLSI technology recently. We proposed a design flow and a FPGA template for implementing generalized C-element (gC) style asynchronous controllers. Utilizing conventional FPGA synthesis tools, self-timed bundled-data function modules can be realized with some effort on timing validation. The proposed design flow with FPGA-based realization approach is a very effective design methodology for rapid prototyping and functionality validation. This work could be useful for the early stage of performance estimation, power reduction exploration, circuits design training, and many other applications regarded asynchronous circuits. In this paper, the proposed FPGA-based asynchronous circuit design flow, a hands-on design tutorial, a generalized C-element template, and a list of synthesized benchmark circuits are documented and discussed in detail.

A new codebook mapping algorithm for artificial bandwidth extension (ABE) is introduced in this paper. We design a wideband line spectrum pair (LSP) codebook which is coupled with the same index as the LSP codebook of a narrowband speech codec. The received narrowband LSP codebook indices are used to directly induce wideband LSP codewords. Thus, the proposed scheme eliminates codebook search processing to estimate the wideband spectrum envelope. We apply the proposed scheme to bandwidth extension in adaptive multi-rate (AMR) compressed domain. Its performance is assessed via the perceptual evaluation of speech quality (PESQ), informal listening tests, and weighted million operations per second (WMOPS) calculations.