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  • System LSI: Challenges and Opportunities

    Tadahiro KURODA  

     
    INVITED PAPER

      Vol:
    E89-C No:3
      Page(s):
    213-220

    Scaling of CMOS Integrated Circuit is becoming difficult, due mainly to rapid increase in power dissipation. How will the semiconductor technology and industry develop? This paper discusses challenges and opportunities in system LSI from three levels of perspectives: transistor level (physics), IC level (electronics), and business level (economics).

  • Thermal Characteristics of Access Cables Composed of Newly Designed Coated Fibers

    Atsuya TAKAHASHI  

     
    PAPER-Optical Fiber for Communications

      Vol:
    E89-B No:3
      Page(s):
    709-714

    The changes in fiber strain and fiber loss with temperature are quantitatively evaluated for 0.5 mm UV-coated fiber and three kind of fiber-optic access cables, for dropping and indoor wiring, employing 0.5 mm UV-coated fiber. Measurements of the fiber strain and loss increase are conducted using a quasi-heterodyne interferometer method and a photon-counting optical-time-domain-reflectmeter, respectively, at 1.3 and 1.55 µ m. From the strain characteristics, the following observations are made: (a) In the temperature range from -40 to 20 the fiber strain followed the cable strain quite closely, thus maintaining a tight cable structure and (b) from 20 to 80, the fiber exhibited a lower strain than the cable strain. Furthermore, no loss increase due to temperature change was observed for the 0.5-mm diameter coated fiber and the three type of optical cables.

  • Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond

    Yoshihide KOMATSU  Yukio ARIMA  Koichiro ISHIBASHI  

     
    PAPER-Soft Error

      Vol:
    E89-C No:3
      Page(s):
    384-391

    This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.

  • High Speed 3D IR Scanner for Home Service Robots

    Jehyuk RYU  Sungho YUN  Kyungjin SONG  Jundong CHO  Jongmoo CHOI  Sukhan LEE  

     
    PAPER-Image/Vision Processing

      Vol:
    E89-A No:3
      Page(s):
    678-685

    This paper introduces the hardware platform of the structured light processing based on depth imaging to perform a 3D modeling of cluttered workspace for home service robots. We have discovered that the degradation of precision and robustness comes mainly from the overlapping of multiple codes in the signal received at a camera pixel. Considering the criticality of separating the overlapped codes to precision and robustness, we proposed a novel signal separation code, referred to here as "Hierarchically Orthogonal Code (HOC)," for depth imaging. The proposed HOC algorithm was implemented by using hardware platform which applies the Xilinx XC2V6000 FPGA to perform a real time 3D modeling and the invisible IR (Infrared) pattern lights to eliminate any inconveniences for the home environment. The experimental results have shown that the proposed HOC algorithm significantly enhances the robustness and precision in depth imaging, compared to the best known conventional approaches. Furthermore, after we processed the HOC algorithm implemented on our hardware platform, the results showed that it required 34 ms of time to generate one 3D image. This processing time is about 24 times faster than the same implementation of HOC algorithm using software, and the real-time processing is realized.

  • Production-Oriented Models for Speech Recognition

    Erik MCDERMOTT  Atsushi NAKAMURA  

     
    PAPER-Speech Recognition

      Vol:
    E89-D No:3
      Page(s):
    1006-1014

    Acoustic modeling in speech recognition uses very little knowledge of the speech production process. At many levels our models continue to model speech as a surface phenomenon. Typically, hidden Markov model (HMM) parameters operate primarily in the acoustic space or in a linear transformation thereof; state-to-state evolution is modeled only crudely, with no explicit relationship between states, such as would be afforded by the use of phonetic features commonly used by linguists to describe speech phenomena, or by the continuity and smoothness of the production parameters governing speech. This survey article attempts to provide an overview of proposals by several researchers for improving acoustic modeling in these regards. Such topics as the controversial Motor Theory of Speech Perception, work by Hogden explicitly using a continuity constraint in a pseudo-articulatory domain, the Kalman filter based Hidden Dynamic Model, and work by many groups showing the benefits of using articulatory features instead of phones as the underlying units of speech, will be covered.

  • Low-Power Hybrid Turbo Decoding Based on Reverse Calculation

    Hye-Mi CHOI  Ji-Hoon KIM  In-Cheol PARK  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E89-A No:3
      Page(s):
    782-789

    As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the Max-log-MAP algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-MAP, that results in a similar BER performance to the log-MAP algorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-MAP turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.

  • Visible Light Communication with LED Traffic Lights Using 2-Dimensional Image Sensor

    Haswani BINTI CHE WOOK  Shinichiro HARUYAMA  Masao NAKAGAWA  

     
    PAPER-Communications

      Vol:
    E89-A No:3
      Page(s):
    654-659

    We propose a new receiving method for an information-providing system that uses LED-based traffic lights as the transmitter. We analyzed the improvements obtained when 2-dimentional image sensor replaced the conventional single-element photodiode. First, we discuss the maximum receiver's field of view (FOV) when using the 2-dimentional image sensor at a particular focal length. We analyzed the best vertical inclination for both lanes and quantified the improvements in terms of the enhancement of received signal-noise ratio (SNR) when different numbers of pixels were applied. Our results indicate that using more pixels increases the received SNR and the service area becomes wider compared to the conventional single-element system. Consequently, receivable information within the service area also increased. We also found that the optimum number of pixels to accomplish a reliable communication system is 5050 because performance degradation occured with a larger number of pixels.

  • Extraction of LRGC Matrices for 8-Coupled Uniform Lossy Transmission Lines Using 2-Port VNA Measurements

    Hyun Bae LEE  Kyoungho LEE  Hae Kang JUNG  Hong June PARK  

     
    PAPER-Electronic Components

      Vol:
    E89-C No:3
      Page(s):
    410-419

    The electrical parameters (88 LRGC matrices) of 8-coupled uniform lossy transmission lines were extracted from 40 S-parameter values measured by using 2-port VNA measurements, where all the ports other than 2 VNA ports were terminated by 50 ohm chip resistors. It was assumed in the extraction step that the transmission lines are weakly-coupled, and that the resistance values of all the termination chip resistors are exactly 50 ohms with the second reflections neglected. Comparison of the extracted LRGC matrix components with those from a commercial 3D field solver revealed on average and a maximum relative difference of 2.45% and 7.66%, respectively. In addition, the time-domain crosstalk voltage waveforms in the measured data and those in the SPICE simulation results using the extracted LRGC parameters agreed very well with the average difference and the maximum relative difference in peak crosstalk voltages of 4.15% and 9.68%, respectively.

  • Analysis of Large-Scale Periodic Array Antennas by CG-FFT Combined with Equivalent Sub-Array Preconditioner

    Huiqing ZHAI  Qiang CHEN  Qiaowei YUAN  Kunio SAWAYA  Changhong LIANG  

     
    PAPER-Antennas and Propagation

      Vol:
    E89-B No:3
      Page(s):
    922-928

    This paper presents method that offers the fast and accurate analysis of large-scale periodic array antennas by conjugate-gradient fast Fourier transform (CG-FFT) combined with an equivalent sub-array preconditioner. Method of moments (MoM) is used to discretize the electric field integral equation (EFIE) and form the impedance matrix equation. By properly dividing a large array into equivalent sub-blocks level by level, the impedance matrix becomes a structure of Three-level Block Toeplitz Matrices. The Three-level Block Toeplitz Matrices are further transformed to Circulant Matrix, whose multiplication with a vector can be rapidly implemented by one-dimension (1-D) fast Fourier transform (FFT). Thus, the conjugate-gradient fast Fourier transform (CG-FFT) is successfully applied to the analysis of a large-scale periodic dipole array by speeding up the matrix-vector multiplication in the iterative solver. Furthermore, an equivalent sub-array preconditioner is proposed to combine with the CG-FFT analysis to reduce iterative steps and the whole CPU-time of the iteration. Some numerical results are given to illustrate the high efficiency and accuracy of the present method.

  • Low-Complexity ICI Cancellation in Frequency Domain for OFDM Systems in Time-Varying Multipath Channels

    Hongmei WANG  Xiang CHEN  Shidong ZHOU  Ming ZHAO  Yan YAO  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E89-B No:3
      Page(s):
    1020-1023

    In this letter, we propose a partial minimum mean-squared error (MMSE) with successive interference cancellation (PMMSESIC) method in frequency domain to mitigate ICI caused by channel variation. Each detection, the proposed method detects the symbol with the largest received signal-to-interference-plus-noise ratio (SINR) among all the undetected symbols, using an MMSE detector that considers only the interference of several neithborhood subcarriers. Analysis and simulations show that it outperforms the MMSE method at relatively high Eb/N0 and its performance is close to the MMSE with successive detection (MMSESD) method in relatively low Doppler frequency region.

  • Design Philosophy of a Networking-Oriented Data-Driven Processor: CUE

    Hiroaki NISHIKAWA  

     
    INVITED PAPER

      Vol:
    E89-C No:3
      Page(s):
    221-229

    To realize a secure networking infrastructure, the author is carrying out CUE (Coordinating Users' requirements and Engineering constraints) project with a network carrier and a VLSI manufacture. Since CUE-series data-driven processors developed in the project were specifically designed to be an embedded programmable component as well as a multi-processor element, particular design considerations were taken to achieve real-time multiprocessing capabilities essentially needed in multi-media communication environment. A novel data-driven paradigm is first introduced with special emphasis on VLSI-oriented parallel processing architectures. Data-driven protocol handlings on CUE-p and CUE-v1 are then discussed for their real-time multiprocessing capability without any runtime overheads. The emulation facility RESCUE (Real-time Execution System for CUE-series data-driven processors) was also built to develop scalable chip multi-processors in self-evolutional manner. Based on emulation results, the latest version named CUE-v2 was realized as a hybrid processor enabling simultaneous processing of data-driven and control-driven threads to achieve higher performance for inline processing and to avoid any bottlenecks in sequential parts of real-time programs frequently encountered in actual time-sensitive applications. Effectiveness of the data-driven chip multi-processor architecture will finally be addressed for lower power consumption and scalability to realize future VLSI processors in the sub-100 nm era.

  • A Novel Mobile Assignment Method for WCDMA Base Station Location Planning

    Li YAO  Chen HE  Junlong LIN  

     
    LETTER-Network Management/Operation

      Vol:
    E89-B No:3
      Page(s):
    978-981

    A novel mobile assignment method based on transmit power and cell load is proposed for WCDMA base station location planning. Experimental results show that, compared with the currently widely used mobile assignment method based on link attenuation, the proposed mobile assignment method is more reasonable and unnecessary base stations are reduced in the planning results.

  • Detection of Moving Cast Shadows for Traffic Monitoring System

    Jeong-Hoon CHO  Dae-Geun JANG  Chan-Sik HWANG  

     
    LETTER-Image/Vision Processing

      Vol:
    E89-A No:3
      Page(s):
    747-750

    Shadow detection and removal is important to deal with traffic image sequences. Cast shadow of vehicle may lead to an inaccurate object feature extraction and erroneous scene analysis. Furthermore, separate vehicles can be connected through shadow. Both can confuse object recognition systems. In this paper, a robust method is proposed for detecting and removing active cast shadow in monocular color image sequences. Background subtraction method is used to extract moving blobs in color and gradient dimensions, and the YCrCb color space is adopted for detecting and removing the cast shadow. Even when shadows link different vehicles, it can detect the each vehicle figure using modified mask by shadow bar. Experimental results from town scenes show that proposed method is effective and the classification accuracy is sufficient for general vehicle type classification.

  • A Hybrid Fine-Tuned Multi-Objective Memetic Algorithm

    Xiuping GUO  Genke YANG  Zhiming WU  Zhonghua HUANG  

     
    PAPER-Numerical Analysis and Optimization

      Vol:
    E89-A No:3
      Page(s):
    790-797

    In this paper, we propose a hybrid fine-tuned multi-objective memetic algorithm hybridizing different solution fitness evaluation methods for global exploitation and exploration. To search across all regions in objective space, the algorithm uses a widely diversified set of weights at each generation, and employs a simulated annealing to optimize each utility function. For broader exploration, a grid-based technique is adopted to discover the missing nondominated regions on existing tradeoff surface, and a Pareto-based local perturbation is performed to reproduce incrementing solutions trying to fill up the discontinuous areas. Additional advanced feature is that the procedure is made dynamic and adaptive to the online optimization conditions based on a function of improvement ratio to obtain better stability and convergence of the algorithm. Effectiveness of our approach is shown by applying it to multi-objective 0/1 knapsack problem (MOKP).

  • Progressive Transform-Based Phase Unwrapping Utilizing a Recursive Structure

    Andriyan Bayu SUKSMONO  Akira HIROSE  

     
    PAPER-Sensing

      Vol:
    E89-B No:3
      Page(s):
    929-936

    We propose a progressive transform-based phase unwrapping (PU) technique that employs a recursive structure. Each stage, which is identical with others in the construction, performs PU by FFT method that yields a solution and a residual phase error as well. The residual phase error is then reprocessed by the following stages. This scheme effectively improves the gradient estimate of the noisy wrapped phase image, which is unrecoverable by conventional global PU methods. Additionally, by incorporating computational strength of the transform PU method in a recursive system, we can realize a progressive PU system for prospective near real-time topographic-mapping radar and near real-time medical imaging system (such as MRI thermometry and MRI flow imager). PU performance of the proposed system and the conventional PU methods are evaluated by comparing their residual error quantitatively with a fringe-density-related error metric called FZX (fringe's zero-crossing) number. Experimental results for simulated and real InSAR phase images show significant, progressive improvement over conventional ones of a single-stage system, which demonstrates the high applicability of the proposed method.

  • Cryptanalysis of Tzeng-Tzeng Forward-Secure Signature Schemes

    Hong WANG  Gang QIU  Deng-Guo FENG  Guo-Zhen XIAO  

     
    LETTER-Information Security

      Vol:
    E89-A No:3
      Page(s):
    822-825

    In PKC'01, Tzeng et al. proposed two robust forward-secure signature schemes with proactive security: one is an efficient scheme, but it requires a manager; the other scheme is a new construction based on distributed multiplication procedures. In this paper, we point out their new distributed multiplication procedure is not secure, thus making the whole new construction insecure. Finally, we present an improved forward-secure signature scheme without a manager.

  • VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation

    Noriyuki MINEGISHI  Junichi MIYAKOSHI  Yuki KURODA  Tadayoshi KATAGIRI  Yuki FUKUYAMA  Ryo YAMAMOTO  Masayuki MIYAMA  Kousuke IMAMURA  Hideo HASHIMOTO  Masahiko YOSHIMOTO  

     
    PAPER-System LSIs and Microprocessors

      Vol:
    E89-C No:3
      Page(s):
    230-242

    An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.025.33 mm2 with six-metal 90-nm CMOS technology.

  • Quarternary Signal Sets for Digital Communications with Nonuniform Sources

    Ha H. NGUYEN  Tyler NECHIPORENKO  

     
    LETTER-Communication Theory and Signals

      Vol:
    E89-A No:3
      Page(s):
    832-835

    This letter considers the signal design problems for quaternary digital communications with nonuniform sources. The designs are considered for both the average and equal energy constraints and for a two-dimensional signal space. A tight upper bound on the bit error probability (BEP) is employed as the design criterion. The optimal quarternary signal sets are presented and their BEP performance is compared with that of the standard QPSK and the binary signal set previously designed for nonuniform sources. Results shows that a considerable saving in the transmitted power can be achieved by the proposed average-energy signal set for a highly nonuniform source.

  • Design of MIMO Communication Systems Using Tapped Delay Line Structure in Receiver Side

    Tetsuki TANIGUCHI  Hoang Huy PHAM  Nam Xuan TRAN  Yoshio KARASAWA  

     
    PAPER-Communications

      Vol:
    E89-A No:3
      Page(s):
    670-677

    This paper presents a simple method to determine weights of single carrier multiple input multiple output (MIMO) broadband communication systems adopting tapped delay line (TDL) structure in receiver side for the effective communication under frequency selective fading (FSF) environment. First, assuming the perfect knowledge of the channel matrix in both arrays, an iterative design method of transmitter and receiver weights is proposed. In this approach, both weights are determined alternately to maximize signal to noise plus interference ratio (SINR) by fixing the weight of one side while optimizing the other, and this operation is repeated until SINR converges. Next, considering the case of uninformed transmitter, maximum SINR design method of MIMO system is extended for space time block coding (STBC) scheme working under FSF. Through computer simulations, it is demonstrated that the proposed schemes achieves higher SINR than conventional method with delay-less structure, particularly for the fading with long duration.

  • A Plan-Generation-Evaluation Framework for Design Space Exploration of Digital Systems Design

    Jun Kyoung KIM  Tag Gon KIM  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E89-A No:3
      Page(s):
    772-781

    Modern digital systems design requires us to explore a large and complex design space to find a best configuration which satisfies design requirements. Such exploration requires a sound representation of design space from which design candidates are efficiently generated, each of which then is evaluated. This paper proposes a plan-generation-evaluation framework which supports a complete process of such design space exploration. The plan phase constitutes a design space of all possible design alternatives by means of a formally defined representation scheme of attributed AND-OR graph. The generation phase generates a set of candidates by algorithmic pruning of the design space in an attributed AND-OR graph with respect to design requirements as well as architectural constraints. Finally, the evaluation phase measures performance of design candidates in a pruned graph to select a best one. A complete process of cache design is exemplified to show the effectiveness of the proposed framework.

11641-11660hit(20498hit)