This paper examines the bit and power allocation problem for orthogonal frequency division multiplexing systems in which the overall transmission power is minimized by constraining the fixed data rate and bit error rate. To provide the optimal allocation with less computational complexity, we propose new bit and power allocation schemes based on the Lagrangian method. Firstly, we propose an initial search range of the bisection search method to find the optimal Lagrangian multiplier efficiently. The simulation results verify that the proposed initial search range guarantees the optimal solution with less computational complexity. Secondly, a new iterative search method for the optimal Lagrangian multiplier is proposed using Newton's search method. The simulation results demonstrate that the proposed scheme has significant computational advantages over the conventional algorithms while providing optimal performance.

This letter describes unequal-power transmission for multiple-input and multiple-output (MIMO) systems with a parallel interference canceller (PIC) applied to a maximum likelihood detector (MLD) or complexity-reduced MLD at the receiver. Unequal-power transmission reduces the possibility that all substreams are incorrectly decoded. Canceling the correctly decoded substreams enables more reliable detection in the next stage. The simulation results demonstrated that unequal-power transmission improves the transmission performance of the PIC applied to MLDs or complexity-reduced MLDs, compared with equal-power transmission cases.

An automatic and efficient algorithm for removal of intensity flicker is proposed. The novel repair process is founded on the block-based estimation and restoration algorithm with regard to luminance variation. It is easily realized and controlled to remove most intensity flicker and preserve the wanted effects, like fade in and fade out.

Hardware prototyping has been widely used for ASIC/SoC verification. This paper proposes a new hardware design verification method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or even weeks, without a break. It compresses the captured data in real time and stores it in a state transition format in memory. Since it records all the transitions, it is effective in finding and fixing errors, even ones that occur rarely or intermittently. It can also be programmed to generate a trigger for a logic analyzer when it detects certain transitions. This is useful for debugging situations where the engineer has trouble finding an appropriate trigger condition to pinpoint the source of errors. We have been using the method in hardware prototyping for ASIC/SoC development for two years and found it useful for system level tests, and in particular for long running tests.

This is commonly thought that CASE tools reduce programming efforts and increase development productivity. However, no paper has provide quantitative data supporting the matter. This paper discusses productivity improvement through the use of an integrated CASE tool system named EAGLE (Effective Approach to Achieving High Level Software Productivity), as shown by various data collected in Hitachi from the 1980s to the 2000s. We have evaluated productivity by using three metrics, l) program generation rate using reusable program skeletons and components, 2) fault density at two test phase, and 3) learning curve for the education of inexperienced programmers. We will show that productivity has been improved by the various facilities of EAGLE.

In this paper, we describe a new interface for a barge-in free spoken dialogue system combining multichannel sound field control and beamforming, in which the response sound from the system can be canceled out at the microphone points. The conventional method inhibits a user from moving because the system forces the user to stay at a fixed position where the response sound is reproduced. However, since the proposed method does not set control points for the reproduction of the response sound to the user, the user is allowed to move. Furthermore, the relaxation of strict reproduction for the response sound enables us to design a stable system with fewer loudspeakers than those used in the conventional method. The proposed method shows a higher performance in speech recognition experiments.

As the technology scaling approaching nano-scale region, variability in device performance becomes a major issue in the design of integrated circuits. Besides the growing amount of variability, the statistical nature of the variability is changing as the progress of technology generation. In the past, die-to-die variability, which is well managed by the worst case design technique, dominates over within-die variability. In present and the future, the amount of within-die variability is increasing and it casts a challenge in design methodology. This paper first shows measured results of variability in three different processes of 0.35, 0.18, and 0.13 µm technologies, and explains the above mentioned trend of variability. An example of modeling for the within-die variability is explained. The impact of within-die random variability on circuit performance is demonstrated using a simple numerical example. It shows that a circuit that is designed optimally under the assumption of deterministic delay is now most susceptible to random fluctuation in delay, which clearly indicates the requirement of statistical design methodology.

In this letter, we propose a new detection method for an OFDM signal distorted by IQ imbalance, and a pilot pattern to estimate the channel associated with IQ imbalance. It is shown by computer simulation that the proposed method can achieve robust detection even when severe IQ imbalance exists in OFDM systems with an input of higher-order constellation.

Random Early Detection (RED), an active queue management scheme, has been recommended by the Internet Engineering Task Force (IETF) for the next generation routers. RED suffers from a number of performance problems, such as low throughput, large delay/jitter, and induces instability in networks. Many of the previous attempts to improve the performance of RED have been based on optimizing the values of the RED parameters. However, results have shown that such optimizations resulted in limited improvement in the performance. In this paper, we propose Double Slope RED (DSRED), a new active queue management scheme to improve the performance of RED. The proposed scheme is based on dynamically changing the slope of the packet drop probability curve as a function of the level of congestion in the buffer. Results show that our proposed scheme results in better performance than original RED.

In this paper, we derive an analytical result for channel holding time distribution in mobile satellite networks under general call holding time distribution.

This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture. With the proposed architecture on the Altera Stratix FPGA, two PPR implementations achieve 6.45 Gbps throughput and 12.78 Gbps throughput, respectively. Compared with the unrolling implementation that achieves a throughput of 22.75 Gbps on the same FPGA, the two PPR implementations improve the memory efficiency (i.e., throughput divided by the size of memory for core) by 13.4% and 12.3%, respectively, and reduce the amount of the memory by 75% and 50%, respectively. Also, the PPR implementation has a up to 9.83% higher memory efficiency than the fastest previous FPGA implementation known to date. In terms of resource efficiency (i.e., throughput divided by the equivalent logic element or slice), one PPR implementation offers almost the same as the rolling implementation, and the other PPR implementation offers a medium value between the rolling implementation and the unrolling implementation that has the highest resource efficiency. However, the two PPR implementations can be implemented on the minimum-sized Stratix FPGA while the unrolling implementation cannot. The PPR architecture fills the gap between unrolling and rolling architectures and is suitable for small and medium-sized FPGAs.

In this paper, we propose a driver identification method that is based on the driving behavior signals that are observed while the driver is following another vehicle. Driving behavior signals, such as the use of the accelerator pedal, brake pedal, vehicle velocity, and distance from the vehicle in front, were measured using a driving simulator. We compared the identification rate obtained using different identification models. As a result, we found the Gaussian Mixture Model to be superior to the Helly model and the optimal velocity model. Also, the driver's operation signals were found to be better than road environment signals and car behavior signals for the Gaussian Mixture Model. The identification rate for thirty driver using actual vehicle driving in a city area was 73%.

The module-wise dynamic voltage and frequency scaling (MDVFS) scheme is applied to a single-chip H.264/MPEG-4 audio/visual codec LSI. The power consumption of the target module with controlled supply voltage and frequency is reduced by 40% in comparison with the operation without voltage or frequency scaling. The consumed power of the chip is 63 mW in decoding QVGA H.264 video at 15 fps and MPEG-4 AAC LC audio simultaneously. This LSI keep operating continuously even during the voltage transition of the target module by introducing the newly developed dynamic de-skewing system (DDS) which watches and control the clock edge of the target module.

A new system identification based method has been proposed for accurate estimation of vocal tract parameters. An often encountered problem in using the conventional linear prediction analysis is due to the harmonic structure of the excitation source of voiced speech. This harmonic characteristic is coupled with the estimation of autoregressive (AR) coefficients that results in difficulties in estimating the vocal tract filter. This paper models the effective voice source from the residual obtained through the covariance analysis in the first-pass which is then used as input to the second-pass least-square analysis. A better source-filter separation is thus achieved. The formant frequencies and corresponding bandwidths obtained using the proposed method for synthetic vowels are found to be accurate up to a factor of more than three (in percent) compared to the conventional method. Since the source characteristic is taken into account, local variations due to the positioning of analysis window are reduced significantly. The validity of the proposed method is also examined by inspecting the spectra obtained from natural vowel sounds uttered by high-pitched female speaker.

In unidentifiable models, the Bayes estimation has the advantage of generalization performance over the maximum likelihood estimation. However, accurate approximation of the posterior distribution requires huge computational costs. In this paper, we consider an alternative approximation method, which we call a subspace Bayes approach. A subspace Bayes approach is an empirical Bayes approach where a part of the parameters are regarded as hyperparameters. Consequently, in some three-layer models, this approach requires much less computational costs than Markov chain Monte Carlo methods. We show that, in three-layer linear neural networks, a subspace Bayes approach is asymptotically equivalent to a positive-part James-Stein type shrinkage estimation, and theoretically clarify its generalization error and training error. We also discuss the domination over the maximum likelihood estimation and the relation to the variational Bayes approach.

In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.

We propose a novel simplified Viterbi equalizer for high symbol rate FWA (Fixed Wireless Access) systems carrying 64QAM signals. Reduced complexity and improved performance are achieved adopting two approaches. The first one is reducing the number of survival paths, taking advantage of the large D/U common in LOS (line of sight) communications. The second one is using a multi-stage process to generate desired signal replicas based on their likelihoods. Computer simulations confirm that the proposed replica generation method offers a performance improvement of about 1 dB and the proposed Viterbi equalizer offers reduced complexity with no performance penalty compared to full Viterbi equalizer.

We present a training algorithm to create a neural network (NN) ensemble that performs classification tasks. It employs a competitive decay of hidden nodes in the component NNs as well as a selective deletion of NNs in ensemble, thus named a pruning algorithm for NN ensembles (PNNE). A node cooperation function of hidden nodes in each NN is introduced in order to support the decaying process. The training is based on the negative correlation learning that ensures diversity among the component NNs in ensemble. The less important networks are deleted by a criterion that indicates over-fitting. The PNNE has been tested extensively on a number of standard benchmark problems in machine learning, including the Australian credit card assessment, breast cancer, circle-in-the-square, diabetes, glass identification, ionosphere, iris identification, and soybean identification problems. The results show that classification performances of NN ensemble produced by the PNNE are better than or competitive to those by the conventional constructive and fixed architecture algorithms. Furthermore, in comparison to the constructive algorithm, NN ensemble produced by the PNNE consists of a smaller number of component NNs, and they are more diverse owing to the uniform training for all component NNs.

Modern digital systems design requires us to explore a large and complex design space to find a best configuration which satisfies design requirements. Such exploration requires a sound representation of design space from which design candidates are efficiently generated, each of which then is evaluated. This paper proposes a plan-generation-evaluation framework which supports a complete process of such design space exploration. The plan phase constitutes a design space of all possible design alternatives by means of a formally defined representation scheme of attributed AND-OR graph. The generation phase generates a set of candidates by algorithmic pruning of the design space in an attributed AND-OR graph with respect to design requirements as well as architectural constraints. Finally, the evaluation phase measures performance of design candidates in a pruned graph to select a best one. A complete process of cache design is exemplified to show the effectiveness of the proposed framework.

This letter considers the signal design problems for quaternary digital communications with nonuniform sources. The designs are considered for both the average and equal energy constraints and for a two-dimensional signal space. A tight upper bound on the bit error probability (BEP) is employed as the design criterion. The optimal quarternary signal sets are presented and their BEP performance is compared with that of the standard QPSK and the binary signal set previously designed for nonuniform sources. Results shows that a considerable saving in the transmitted power can be achieved by the proposed average-energy signal set for a highly nonuniform source.