A highly stable oven-controlled crystal oscillator (OCXO) with low phase-noise characteristics has been developed using a dual-mode SC-cut quartz crystal oscillator. The OCXO uses a conventional oven-control system for coarse compensation and a digital-correction system, which uses B-mode signal in an SC-cut resonator as a temperature sensor, for fine compensation. Combining these two forms of compensation greatly improves the stability of the C-mode frequency without requiring a double-oven system. The experimental results indicated that the frequency stability of the proposed OCXO, including the frequency-temperature hysteresis, is ten times better than that of a conventional, free-running OCXO. The results also indicated that the proposed OCXO has good frequency retraceability and low phase-noise characteristics.

Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.

Today, an ultra-high capacity transmission system based on N40 Gb/s channel rate is the most promising approach to achieve multi-terabit/s of capacity over a single fiber. We have demonstrated 5.12 Tbit/s transmission of 128 channels at 40 Gbit/s over 3100 km and 10.24 Tbit/s transmission of 256 channels at 42.6 Gbit/s (using FEC) over 100 km, based on four main technologies: 40 Gbit/s electrical time-division multiplexing (ETDM), vestigial sideband demultiplexing (VSB), advanced amplifier technology including Raman amplification and TeraLightTM fiber. A record spectral efficiency of 1.28 bit/s/Hz is applied to achieve 10.24 Tbit/s transmission within the C- and L-band.

In this study, a hybrid genetic algorithm/neural network with fuzzy logic controller (NN-flcGA) is proposed to find the global optimum of reliability assignment/redundant allocation problems which should be simultaneously determined two different types of decision variables. Several researchers have obtained acceptable and satisfactory results using genetic algorithms for optimal reliability assignment/redundant allocation problems during the past decade. For large-size problems, however, genetic algorithms have to enumerate numerous feasible solutions due to the broad continuous search space. Recently, a hybridized GA combined with a neural network technique (NN-hGA) has been proposed to overcome this kind of difficulty. Unfortunately, it requires a high computational cost though NN-hGA leads to a robuster and steadier global optimum irrespective of the various initial conditions of the problems. The efficacy and efficiency of the NN-flcGA is demonstrated by comparing its results with those of other traditional methods in numerical experiments. The essential features of NN-flcGA namely, 1) its combination with a neural network (NN) technique to devise initial values for the GA, 2) its application of the concept of a fuzzy logic controller when tuning strategy GA parameters dynamically, and 3) its incorporation of the revised simplex search method, make it possible not only to improve the quality of solutions but also to reduce computational cost.

A new logic-in-memory circuit is proposed for a fine-grain pipelined VLSI system. Dynamic-storage elements are distributed over a logic-circuit plane. A functional pass gate is a key component, where a linear summation and threshold function are merged compactly using charge-storage and charge-coupling effect with a DRAM-cell-based circuit structure. The use of dynamic logic based on pass-transistor network using functional pass gates makes it possible to realize any logic circuits compactly with small power dissipation. As a typical example, a 54-bit pipelined multiplier is implemented by using the proposed circuit technology. Its power dissipation and chip area are reduced to about 63 percent and 72 percent, respectively, in comparison with those of a corresponding binary CMOS implementation under 0.35-µm CMOS technology.

Media processing has become one of the dominant computing workloads. In this context, SIMD instructions have been introduced in current processors to raise performance, often the main goal of microprocessor designers. Today, however, designers have become concerned with the power consumption, and in some cases low power is the main design goal (laptops). In this paper, we show that SIMD ISA extensions on a superscalar processor can be one solution to reduce power consumption and keeping a high performance level. We reduce the average power consumption by decreasing the number of instructions, the number of cache references, and using dynamic power management to transform the speedup in performance in power consumption reduction.

This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.

A Wireless Sensor Network (WSN, for short) is a distributed system consisting of n sensor nodes and a base station. In this paper, we propose an energy-efficient protocol to initialize the sensor nodes in a WSN, that is, to assign a unique ID to each sensor node. We show that if an upper bound u on the number n of sensor nodes is known beforehand, for any f 1 and any small µ (0<µ<1), a WSN without collision detection capability can be initialized in O((log (1/µ) + log f)u1+µ) time slots, with probability exceeding 1-(1/f), with no sensor node being awake for more than O(log (1/µ)+ log f) time slots.

This paper proposes list Viterbi equalizers (LVEs) that use two kinds of metric criteria for wide-spread time-dispersive channels to achieve a good trade-off between complexity and bit error rate (BER) performance. For Viterbi equalization employing a state-reduction algorithm, the modified metric criterion proposed by Ungerboeck is not always equivalent to the squared Euclidean distance metric criterion. This paper proposes the following two schemes for the LVE: (1) to combine two kinds of metric criteria like combining diversity; (2) to select the metric criterion like selection diversity according to the channel impulse response. Finally, computer simulation shows that the proposed schemes improve BER performance on wide-spread frequency selective fading channels, even if the proposed schemes have smaller complexity than the conventional one.

This paper investigates the accepting powers of one-way alternating and deterministic multi-counter automata operating in realtime. We partially solve the open problem posed in [4], and show that for each k1, there is a language accepted by a realtime one-way deterministic (k+3)-counter automaton, but not accepted by any realtime one-way alternating k-counter automaton.

A fully on-chip active guard band circuit is proposed. The proposed circuit is mainly composed of current mirrors and based on a DC bias technique. HSPICE simulations and experiment results confirm the validity of the proposed active guard band circuit.

In this paper, we address the key enabling technologies for long-span WDM transmissions at 40 Gbit/s. Experimental results of 1.28 Tbit/s (32 40 Gbit/s) unrepeatered transmission over 240 km of conventional 80-µm2 NDSF will be reported. Bi-directional pumped distributed Raman amplification has allowed a record unrepeatered WDM transmission distance over this fibre type, without using effective-area-enlarged fibres or remotely pumped EDFAs.

In this paper, we propose a probabilistic approach to derive an approximate polyhedral description from range data. We first compare several least-squares-based methods for estimation of local normal vectors and select the most robust one based on a reasonable noise model of the range data. Second, we extract the stable planar regions from the range data by examining the distributions of the local normal vectors together with their spatial information in the 2D range image. Instead of segmenting the range data completely, we use only the geometries of the extracted stable planar regions to derive a polyhedral description of the range data. The curved surfaces in the range data are approximated by their extracted plane patches. With a probabilistic approach, the proposed method can be expected to be robust against the noise. Experimental results on real range data from different sources show the effectiveness of the proposed method.

We present a state-space approach to the problem of designing a parallel feedforward compensator (PFC), which has the same dimension of the input i.e. input-dimensional, for a class of non-square linear systems such that the closed-loop system is strictly passive. For a non-minimum phase system or a system with high relative degree, passification of the system cannot be achieved by any other methodologies except by using a PFC. In our scheme, we first determine a squaring gain matrix and an additional dynamics that is connected to the system in a feedforward way, then a static passifying control law is designed. Consequently, the actual feedback controller will be the static control law combined with the feedforward dynamics. Necessary and sufficient conditions for the existence of the PFC are given by the static output feedback formulation, which enables to utilize linear matrix inequality (LMI). Since the proposed PFC is input-dimensional, our design procedure can be viewed as a solution to the low-order dynamic output feedback control problem in the literature. The effectiveness of the proposed method is illustrated by some numerical examples.

Much has been said and written about the changes in analog IC technology such as shrinking line widths, vanishingly low supply voltages, severe power limitations, and digital noise. But beyond these technology changes and their subsequent methodology changes, a far more subtle revolution is happening in the nature of the profession itself. Technology, software, and product evolution have all conspired to create a new kind of analog IC designer, one very different from the IC designers of the past.

An LSI has been fabricated and measured to demonstrate feasibility of VDD-hopping scheme in an embedded system level by executing MPEG4 CODEC. In the VDD-hopping, supply voltage of a processor is dynamically controlled by a hardware-software cooperative mechanism depending on workload of the processor. When the workload is about a half, the VDD-hopping is shown to reduce power to less than a quarter compared to the conventional fixed-VDD scheme. The power saving is achieved without degrading real-time features of MPEG4 CODEC.

The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (Vdd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.

This paper presents an explicit analysis of the output error power in wideband sampling systems with finite aperture time in the presence of sampling jitter. Sampling jitter and finite aperture time affect the ability of wideband sampling systems to capture high-frequency signals with high precision. Sampling jitter skews data acquisition timing points, which causes large errors in high-frequency (large slew rate) signal acquisition. Finite sampling-window aperture works as a low pass filter, and hence it degrades the high-frequency performance of sampling systems. In this paper, we discuss these effects explicitly not only in the case that either sampling jitter or finite aperture time exists but also the case that they exist together, for any aperture window function (whose Fourier transform exists) and sampling jitter of Gaussian distribution. These would be useful for the designer of wideband sampling data acquisition systems to know how much sampling jitter and aperture time are tolerable for a specified SNR. Some experimental measurement results as well as simulation results are provided as validation of the analytical results.

The analog inverter for realization of the NOT function is the indispensable circuit element in the voltage-mode analog and digital signal processing. In this paper, we propose a novel analog inverter composed of only two neuron-MOS transistors. The analog inverter has the weighted negative feedback mechanism to operate both of neuron-MOS transistors under the saturation region in all input ranges. In verification using HSPICE simulations, the analog inverter performs the high linearity with errors of approximately 40 [mV] in all input ranges, particularly errors of less than 19 [mV] in more than 90% of input ranges. And, the maximum power consumption of the analog inverter is less than 1.5 [µW] although a peak of a standard CMOS inverter is around 30 [µW] under the supply voltage of 3.0 [V]. These good stability and results are produced by the negative feedback. Furthermore, fabrication costs of the analog inverters can be kept at the minimum because neuron-MOS transistors can be actualized in a conventional CMOS process without any additional process. For applications of the analog inverter, the voltage comparator with high noise margins is designed and is applied to the two-input MAX and the two-input MIN circuits in the voltage-mode. The MAX and the MIN circuits for realization of the MAX and the MIN functions, respectively, can be composed of total ten transistors each. They also perform well in verifications. On the basis of the proposed circuits, almost all of voltage-mode multi-valued logic circuits with high-performance can be realized like present binary logic systems. And, the proposed circuits can give full play to the high linearity and advantages for the arbitrary transformation of signal forms in the analog signal processing such as the fuzzy control.

The mobile computing system is a set of functions on a distributed environment organized to support mobile hosts. In this environment, mobile hosts should be able to move without any constraints and should remain connected to the network even while moving. Also, they should be able to get necessary information regardless of their current location and time. Distributed mutual exclusion methods for supporting distributed algorithms have hitherto been designed for networks only with static hosts. However, with the emergence of mobile computing environments, a new distributed mutual exclusion method needs to be developed for integrating mobile hosts with underlying distributed systems. In the sense, many issues that should be considered stem from three essential properties of mobile computing system such as wireless communication, portability, and mobility. Thus far, distributed mutual exclusion methods for mobile computing environments were designed based on a token ring structure, which has the drawback of requiring high costs in order to locate mobile hosts. In this paper, we propose not only a distributed mutual exclusion method that can reduce such costs by structuring the entire system as a tree-based logical structure but also recovery schemes that can be applied when a node failure occurs. Finally, we evaluate the operation costs for the mutual exclusion scheme and the recovery scheme.