In this paper, we give an algorithm for the node-to-set disjoint paths problem in rotator graphs with its evaluation results. The algorithm is based on recursion and it is divided into cases according to the distribution of destination nodes in classes into which all the nodes in a rotator graph are categorized. The sum of the length of paths obtained and the time complexity of the algorithm are estimated and verified by computer simulation.

We show some results concerning the number of solutions of the equation y+Ax=b (yTx=0, y0, x0) which plays a central role in the dc analysis of transistor circuits. In particular, we give sufficient conditions for the equation to possess exactly 2l (ln) solutions, where n is the dimension of the vector x.

Sector antennas provide many advantages such as when combined with a narrow beam antenna, they become particularly effective in achieving high-speed wireless communication systems and they aid in simplifying the structure. These antennas have a drawback in that as the number of sectors increases, the antenna size rapidly increases. Therefore, downsizing the sector antenna has become a major research topic. A promising candidate is utilizing a phased-array type antenna; however, this antenna requires a phase-shifter circuit for beam scanning and generally the feeding circuit for this type of antenna is very complicated. To address these issues, we propose a self-selecting feeding circuit that is controlled by the same control circuit and is operated similarly to the conventional single port n-th throw (SPNT) switch. We fabricated a small cylindrical 12-sector antenna at 19 GHz employing the proposed feeding circuit for verification purposes. Furthermore, this paper clarifies the design method of this feeding circuit where the antenna diameter is 71 mm, and the results clearly show that the gain is more than 12 dBi.

A flexible noise generation algorithm using DCT is proposed. The proposed method outperforms the conventional methods when a noise model requires complicated PSD (Power Spectral Density) specifications. Also, it is shown that the proposed system can be used for the test of VDSL (Very high-speed Digital Subscriber Line).

The MUSIC (Multiple Signal Classification) technique with the circular array can estimate both elevational and azimuthal direction-of-arrival (DOA). This conventional method can not distinguish coherent signals, therefore, it can not estimate proper DOA in the presence of coherent signals. On the other hand, limited as to uniformly spaced linear arrays, the spatial smoothing technique is shown to be effective approach in decorrelating coherent signals. This scheme can not be applied directly to the nonlinear arrays. To overcome the coherent signal nonseparation problem in the nonlinear arrays, the approach using a linear interpolation technique has been proposed. However, this approach provides DOA estimates in one dimensional. In our proposed method, we use not only a linear interpolation technique for the circular array but also the symmetry of the circular array. The computer simulation is performed to demonstrate the usefulness of our method. As its result shows, the method can perform well even in the presence of coherent signals.

Particulate media composed of very small particles were studied to determine high-density recording performance and thermal stability. Studied media included metal particulate media with mean particle length of 71, 102 and 148 nm, and Ba ferrite particulate media with mean diameter of 22, 28 and 50 nm. Using a loss-term simulation program, taking into account gap-loss, spacing-loss and particle length loss, the recording capability (D20 of 265 kFRPI for MP and 290 kFRPI for Ba ferrite media) was estimated. Thermal stability was evaluated from magnetization time decay measurements. It was found that MP media with large Ku values and 71 nm particles were satisfactorily stable, and the particle volume is still large enough in respect of thermal stability. However, 22-nm Ba ferrite media were less stable, primarily because of small Ku values and particle volume. It was also clarified that positive inter-particle interaction accelerates magnetization time decay, in the presence of a large reverse field.

This paper introduces a switched-voltage delay cell with differential inputs. It can be used as a building block for a range of analogue functions such as voltage-to-frenquency converter, A/D converter, etc. Applications incorporating the delay cell are presented. The performances are verified by simulations on PSpice.

This paper proposes a hardware configuration using only single pole dual throw (SPDT) switches to realize the previously proposed automatic calibration method using transmitting signals (ACT) for the adaptive array in TDD communication systems. The proposed configuration obtains the same calibration values as the conventional ACT does while reducing the number of switch branches. The transmission pattern using the proposed calibration method is also presented based on an experimental adaptive array testbed in an actual microcell environment. The experimental results show that the ideal radiation pattern formation is achieved by employing the proposed calibration method in an environment with a moving terminal station and where arriving co-channel interference exists.

In this paper we describe a multicast routing algorithm, which builds upon mobile multicast agents of an ad-hoc network. Mobile multicast agents (MMAs) form a virtual backbone of an ad-hoc network and they provide multicast tree discovery, multicast tree maintenance and datagram delivery. First, we construct a cluster-spine hierarchy structure for an ad-hoc network. Second, we propose a multicast routing algorithm, which is inspired by Ad-hoc On-Demand Distance Vector (AODV) routing protocol. The results show that the MMA multicast algorithm can simplify the multicast tree discovery, reduce control overhead of the network, and increase the total network throughput, in comparison with general AODV multicast operation. We also overcome the deficiency of CBRP multicast routing, which places much burden on cluster heads.

The design and implementation of a novel English writing environment is described. The system integrates modern computer and networking technologies with analytical tools from linguistics and language pedagogy to construct an advanced English writing environment. The system is not only suitable for students in learning English, but also of benefit to teachers in making comments and detecting learners' common difficulties. Furthermore, the collected essays from students and comments from teachers constitute a useful learner corpus. This is also of benefit to researchers in analyzing learners' persistent errors. In order to allow global access from the Internet, the system is web-based. Users, for example, students, teachers, and researchers, may access the system through web browsers. The system was developed in a cooperative effort of Computers And Networking (CAN) laboratory and the Research in English Acquisition and Pedagogy (REAP) Group at Tamkang University. The system has been piloted by six English faculty members at Tamkang University and is currently being used in five high schools in Taiwan. The learner corpus currently consists of over 800,000 word tokens of learners' writing.

This paper proposes resolution enhancement techniques for high-speed multi-stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/stage multiplying digital-to-analog converter. The proposed techniques increase ADC resolution and simultaneously minimize chip area, power dissipation, and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated. The resolution of the proposed ADC can be extended furthermore by combining a conventional commutated feedback-capacitor switching scheme with the digital-domain self calibration.

In this paper, a CMOS down-conversion double-balanced mixer is presented with the modified low voltage design technique. The frequencies of the radio frequency (RF) signal, local oscillator (LO) and intermediate frequency (IF) are 2.4 GHz, 2.3 GHz and 100 MHz, respectively. Measurement results of the proposed mixer exhibit 6.7 dB of conversion gain, -18 dBm of input 1 dB compression point (P-1 dB), -8 dBm of input-referred third-order intercept point (IIP3), and 14.7 dB single-side band (SSB) noise figure (NF) while applying -8 dBm LO power and consumes 3.3 mA from 1.8 V supply voltage. It can provide 0.7 dB conversion gain when the supply voltage reduces to 1.3 V. This mixer was fabricated in a 0.35 µm 1P4M standard digital CMOS process and the die size is 1.5 1.1 mm2.

The Tropical Rainfall Measuring Mission (TRMM) is a United States-Japan joint project to measure rainfall from space. The first spaceborne rain radar is aboard the TRMM satellite. Rain/no-rain discrimination for the TRMM provides useful information for on-line data processing, storage, and post-processing analysis. In this paper, rain/no-rain discrimination for the TRMM has been validated through simulation and theory for the no-rain condition and by comparison with the ground-based radar data for rain conditions.

A unified polyphase representation of analysis and synthesis filter banks is introduced in this paper, and then the efficient implementation on digital signal processors (DSP) is investigated. Especially, the number of memory accesses, power consumption, processing accuracy and the required instruction cycles are discussed. Firstly, a unified representation is given, and then two types of procedures, SIMO system-based and MISO system-based procedures, are shown, where SIMO and MISO are abbreviations for single-input/multiple-output and multiple-input/single-output, respectively. These procedures are compared to each other. It is shown that the number of data load in SIMO system-based procedure is a half of that in MISO system-based procedure for two-channel filter banks. The implementation of M-channel filter banks is also discussed.

Linear adaptive digital filters are applied to various fields for their simplicity in the design and implementation. Considering many kinds of nonlinearities inherent in practical systems, however, nonlinear adaptive filtering will be more desirable. This paper presents a design method for multi-input single-output nonlinear adaptive digital filters using recurrent neural networks. Furthermore, in comparison with this method and the method based on the conventional linear theory, if the proposed method is used, better results can be obtained, and, it is possible that the learning efficiency is improved, because the parallel learning is carried out in this method. Finally, the results of computer simulation are presented to illustrate the effectiveness of the proposed method.

A new approach to design variable IIR digital filters by using a cascade of N identical individual filters of any order n is proposed in this paper. First, the approximation method for lowpass filter specifications is outlined, then the general limitations of the new method are investigated and a compact formula is derived. Next, the limitations for the main canonic approximations (Butterworth, Chebyshev and Elliptic) are investigated and compared and convenient expressions for design and evaluation are obtained. New first- and second-order filter sections, permitting very easy tuning of the cutoff frequency by recalculating and reprogramming of a single multiplier coefficient value, are developed and the design and tuning strategies for highpass, bandpass and bandstop filters are proposed. Finally design examples are given and the sound superiority of the new method compared to other known is demonstrated experimentally.

Although many successful asynchronous control circuit synthesis methods are available, it is still unwieldy to conceive and describe the behaviors of a number of controllers which constitute a control unit of a target system manually. In this paper, an automatic and systematic method to derive an efficient asynchronous control unit from a system specification, a control data flow graph (CDFG), is suggested. In order to acquire an asynchronous control unit of acceptable quality, a new process-oriented method is proposed. In this method, the resulting asynchronous control unit has complete separation of 'execution controllers' and 'execution order controllers' according to the hierarchical decomposition of a given CDFG. This distributive feature leads to a significant improvement in area, performance, implementability and synthesis time for the derived asynchronous control units.

Detection of nonlinearly distorted signals is an essential problem in telecommunications. Recently, neural network combined conventional equalizer has been used to improve the performance especially in compensating for nonlinear distortions. In this paper, the self-organizing map (SOM) combined with the conventional symbol-by-symbol detector is used as an adaptive detector after the output of the decision feedback equalizer (DFE), which updates the decision levels to follow up the nonlinear distortions. In the proposed scheme, we use the box distance to define the neighborhood of the winning neuron of the SOM algorithm. The error performance has been investigated in both 16 QAM and 64 QAM systems with nonlinear distortions. Simulation results have shown that the system performance is remarkably improved by using SOM detector compared with the conventional DFE scheme.

Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.

We analyze electron transport of silicon single-electron transistors (Si SETs) with an ultra-small quantum dot using a master-equation model taking into account the discreteness of quantum levels and the finiteness of scattering rates. In the simulated SET characteristics, aperiodic Coulomb blockade oscillations, fine structures and negative differential conductances due to the quantum mechanical effects are superimposed on the usual Coulomb blockade diagram. These features are consistent with the previously measured results. Large peak-to-valley current ratio of negative differential conductances at room temperature is predicted for Si SETs with an ultra-small dot whose size is smaller than 3 nm.