We propose a new concept of network dimensioning, which is based not only on the grade of service but also on profit. In traditional network dimensioning methodology, the number of circuits on links is designed under a cost-minimization concept with grade of service constraints. Recently, telecommunication markets have become very large and competitive; therefore, we believe that a profit viewpoint is now essential. However, it is difficult to calculate profit in almost all the dimensioning methods currently used, because they mainly employ peak-hour traffic data, while profit depends on all the hourly traffic data which contain both peak and off-peak data. In this paper, we propose using all the hourly traffic data in network dimensioning. From these data and telephone charges for each hour, revenues will be estimated. On the other hand, facility costs will be estimated from the number of circuits. Finally, we can estimate profit from the difference between revenues and facility costs. Focusing on both quality and profits in network dimensioning leads to more advanced quality management and quality control in telecommunications networks than with traditional methodology. This paper outlines a dimensioning method based on profit, and describes its properties, some applications of it, and summarizes further studies.

In this paper, we present a method for extracting the Japanese printed characters from unformatted document images. This research takes into account the multiple general features specific to the Japanese printed characters. In our method, these features are thought of as the constraints for the regions to be extracted within the constraint satisfaction approach. This is achieved by minimizing a constraint function estimating quantitative satisfaction of the features. Our method is applicable to all kinds of the Japanese documents because it is no need of a priori knowledge about the document layout. We have favorable experimental results for the effectiveness of this method.

A low power bus architecture with Local and Global Charge-Recycling Bus (Local-CRB and Global-CRB) techniques, featuring virtual stacking of the individual bus-capacitance and the dummy capacitor into a series configuration between supply voltage and ground, has been proposed. These Local and Global CRB schemes make it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultra multi-bit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance or the dummy capacitor, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, if employing the combination of those CRB schemes in a practical chip, the ultra-high data rate of 25 Gb/s can be achieved while maintaining the power dissipation to be less than 300 mW at Vcc3.6 V for the bus width of 512 bit with the bus-capacitance of 14 pF per bit operating at 50 MHz.

This paper proposes a novel updating technique, dynamically updating, for achieving extension or modification of functions in a distributed system. Usual updating technique requires synchronous suspension for multiple processes for avoiding unspecified reception caused by the conflict of different versions of processes. Thus, this technique needs very high overhead and it must restrict the types of distributed systems, to which it can be applied, to RPC (remote procedure call) type or client-server type. Using the proposed dynamically updating technique, updating management can be invoked asynchronously by each process with assurance of correct execution of the system, i.e., the system can cope with the effect of unspecified reception caused by mixture of different version processes. Therefore, low overhead updating can be achieved in partner type distributed systems, that is more general type including communications systems or computer networks. Dynamically updating technique is implemented by using a novel distributed algorithm that consists of group communication, checkpoint setting, and rollback recovery. By using the algorithm proposed in this paper, rollback recovery can be achieved with the lowest overhead, i.e., a set of checkpoint determines the last global state for consistent rollback recovery and a set of processes that need to rollback simultaneously is the smallest one. This paper also proves the correctness of the proposed algorithm.

Recent advances of processing speed and window systems in computers, especially workstations, accelerate multi-media data processing (MMDP). Then, a variety of data such as numerics, characters, voice, video, animation and so on, are processed concurrently in a workstation. In data processings, concurrent execution of transactions is a key to improve through-puts. However, concurrent execution without concurrency control may cause inconsistent results. Thus, the concurrency control must be introduced in such systems. However, in MMDP it is ineffective to adopt previous concurrency control methods for ordinal databases since multi-media data are huge and possess a real-time property. This paper discusses concurrency control for MMDP. We propose some new concepts for MMDP, and define a new serializability class called Permissible Serializability which provides high concurrency in MMDP compared with ordinal classes. Then, we propose a concurrency control algorithm TYPE for the Permissible Serializability, and show some simulation results.

The Manchester Dataflow Machine (MDFM) works with tasks of size equal to one single instruction. This fine granularity aims at exploring all parallelism at the instruction level. However, this project decision increases the instruction communication cost, which ends up to jam the interconnection network and reduces the system performance. One way to skirt this problem is to adopt variable size tasks instead of working with such small task size. In this paper, in order to study whether or not the usage of such variable size tasks in the MDFM architecture contributes to the improvement of the performance, some simulations by toy programs take place. In the simulation, variable size tasks are realized by packing the sequential instruction stretches into one task. To manage this packing, the Sequential Block (SB) technique is developed. The simulation of those packed and unpacked programs give an outline of advantages and disadvantages of working with variable size tasks, and how the SB technique should be implemented in the system.

We report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1-µm gate HEMT was 430 mS/mm and the peak-to-valley current ratio of the RTD was 5.1. Using the integrated structure, we demonstrate basic digital circuits to show low power characteristics of an RTD-load inverter and a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V. The static power consumption was 7.3 µW/gate for the inverter and 3.0 µW for memory cell.

This paper studies congestion control schemes for integrated variable bit-rate (VBR) video and data communications, where the quality of service (QOS) of each medium needs to be satisfied. In order to control congestion, we exert here either dynamic resolution control or QOS control. The dynamic resolution control scheme in this paper dynamically changes the temporal or spatial resolution of video according to the network loads. The QOS control scheme here assigns a constant capacity of buffer to each connection and determines the video resolution in order to guarantee the QOS of each medium at the connection establishment. The performance of these schemes is evaluated through simulation in terms of throughput, video frame delay probability distribution, and video frame loss rate. We also examine the effects of priority scheduling and packet discarding on the performance. Numerical results indicate that both dynamic resolution and QOS control attain low delay jitters as well as large video and data throughput. In particular, the QOS control is shown to be more suitable for integrated VBR video and data communications.

With the development in portable electronic equipment, the demand for secondary batteries of high energy density is increasing. Recently, nickel metal hydride secondary batteries (Ni/MH) are expanding the market, and lithium ion secondary batteries have been newly developed and commercialized. This paper describes in detail Ni/MH and lithium ion secondary batteries, and reports on their development state and characteristics.

Board-to-board signal transmission in a rack system is affected by various types of noise. Signal transmission capability is evaluated on the basis of physical construction parameters and signal conditions, such as rise time and amplitude. This paper examines noise in a rack system and shows that the maximum single-ended transmission capability is 100Mbps when pin-type connectors are used with a signal/ground pin assignment ratio of 1/1.

This paper reports an overload control method for the Intelligent Network (IN). The IN, which is being investigated as a future communication network, facilitates both rapid introduction of new services and easy modification of existing services. In the IN, the call processing functions and data needed to achieve IN services are distributed over several nodes. Therefore, traffic demand for the various services may cause varying patterns of node overloads. It is therefore important to develop effective overload control methods and to evaluate their characteristics. We propose an overload control method and evaluate its characteristics in comparison with other methods under various overload traffic patterns with a network simulator that models all nodes and their relationships in the IN. In particular, we focus on three aspects of overload control: how can high throughput be maintained, how can an overloaded node be stabilized, and how can fair access be guaranteed.

Device models for a laser diode, photodetector, MESFET, HEMT, bipolar transistor, diode, and resistor are proposed and are implemented in a commercial mixed-signal simulator along with models for an optical fiber, an external optical modulator, and a pulse pattern generator. The validity of the models is confirmed by comparing simulated and experimental results. The performance of a mixed photonic/electronic circuit, which is determined by a large-signal waveform and the device noises, is estimated by the present analysis method.

The performance of the hybrid-ARQ scheme with a convolutional code, in which the retransmission criterion is based on an estimated decoding error rate, is evaluated for moderately time-varying channels. It is shown by computer simulations that the simple average diversity combining scheme can almost attain the same performance as the optimally weighted diversity combining scheme. For the whole and partial retransmission schemes with the average diversity combining, the theoretical bounds of throughput and bit error rate are derived, and it is shown that their bounds are tight and the treated schemes can attain a given error rate with good throughput for moderately time-varying channels. Furthermore, the throughput is shown to be improved by the partial retransmission scheme compared with the whole retransmission scheme.

Circuit access control is a traffic control technique of rejecting calls arriving at a group of specified circuits to make the group free at a target scheduled time so that the capacity may be dynamically reallocated to serve other traffic demand. This technique plays an important role for resource allocation control in state-of-the-art capacity reconfigurable networks as well as for switching calls on a reserved basis in the ISDNs. In this paper, we present a novel adaptive scheme for circuit access control in order to overcome the inefficiency of the conventional deterministic scheme. The presented scheme is based only on knowledge about service time and bandwidth characteristics of calls. The transitional behavior of the circuit group under the scheme is analyzed, and the gain in utilization achieved by the adaptive scheme is examined. We treat a model of the circuit group shared by multi-slot calls with different service times, and describe the results of the transient analysis and the approximation method for evaluating the gains.

We have done a computer search for solutions of the equation x3y3z3n in the range max (|x|, |y|, |z|) 3414387 and 0 n 1000. We have discovered 21 new integer solutions for n {39, 143, 180, 231, 312, 321, 367, 439, 462, 516, 542, 556, 660, 663, 754, 777, 870}. As a result, there are 52 values of n (except n 4 (mod9)) for which no solutions are found.

This paper proposes a universal structure for STM-N(N=1, 2, 3, ) multiplex line terminals that only utilizes N chips CMOS LSIs for Section OverHead (SOH) processing. The uniquely configured LSIs are applicable to any STM-N line terminal equipment. Reasonable frame alignment performance attributes, such as the maximum average reframe time, false in-frame time, out-of-frame detection time, and misframe time, are calculated for the configuration. A prototype SOH processing LSI built on 0.8m BiCMOS technology successfully realizes the functions needed for multiplex section termination. The STM-64 frame is also demonstrated using the proposed circuit configuration and prototype LSIs.

We discuss properties of acyclic graph evolution driven by node-firing. The research background and basic concepts of acyclic graph evolution are from the mutual exclusion problem in distributed environments. We proposed in our previous work a mutual exclusion protocol which is based on the notion of evolution trajectories of acyclic graphs. In this paper, we analyze firing concurrency and periodicity of the acyclic graph evolution, from graph theoretical point of views, and investigate topological conditions for assuring the number of firable nodes below a some fixed constant, at any instance of the evolution trajectory. A marked graph, a subclass of Petri nets, is often utilized as a proof tool in analysis.

We propose a nonlocal impact ionization model applicable for the drain region where electric field increases exponentially. It is expressed as a function of an electric field and a characteristic length which is determined by a thickness of gate oxide and a source/drain junction depth. An analytical substrate current model for n-MOSFET is also derived from the new nonlocal impact ionization model. The model well explains the reason why the theoretical characteristic length differs from empirical expressions used in a pseudo two-dimensional model for MOSFET's. The nonlocal impact ionization model implemented in a device simulator demonstrates that the new model can predict substrate current correctly in the framework of drift-diffusion model.

We developed an eye-contact technique using a blazed half-transparent mirror (BHM), which is a micro-HM array arranged on the display surface, to make a compact eye-contact videophone. This paper describes a new BHM structure that eliminates ghosts and improves image quality. In the new BHM, the reflection and transmission areas are separated to exclude ghosts from appearing in the captured image. We evaluated the characteristics of the captured and displayed images. The results show that the contrast ratio of the captured image and the brightness of both captured and displayed images are much better than with the previous BHM.

A parallel overlapping preconditioner is applied to ICCG method and the effect of the parallel preconditioning on the convergence of the method is investigated by solving large scale block tridiagonal linear systems arising from the discretization of Poisson's equation. Compared with the original ICCG method, the parallel preconditioned ICCG method can solve the problems in high parallelism with slight increasing the number of iterations. Furthermore, the speedup and the efficiency are evaluated for the parallel preconditioned ICCG method by substituting the experimental results into formulae of complexity. For example, when a domain of simulation is discretized on a 250250 rectangular grid and the preconditioner is divided into 249 smaller ones, its speedup is 146.3 with the efficiency 0.59.