A radial line slot antenna (RLSA) is a high gain and high efficiency planar antenna proposed for DBS subscribers. Spirally arrayed slots are excited by a cylindrical wave with the rotational symmetry. In a small sized antenna where large slot coupling is adopted, aperture efficiency reduction due to rotational asymmetry associated with a spiral arrangement of the slots becomes notable. Authors proposed a RLSA with a concentric slot arrangement excited by a rotating mode in order to enhance the rotational symmetry. This is the first report of the normal operation of a rotating mode RLSA fed by a cavity resonator. The experiments confirm the basic operation of this novel antenna; the gain of 27.8dBi and the efficiency of 68% is measured at 11.85GHz for the RLSA with 0.24mφ.

The performance of the hybrid-ARQ scheme with a convolutional code, in which the retransmission criterion is based on an estimated decoding error rate, is evaluated for moderately time-varying channels. It is shown by computer simulations that the simple average diversity combining scheme can almost attain the same performance as the optimally weighted diversity combining scheme. For the whole and partial retransmission schemes with the average diversity combining, the theoretical bounds of throughput and bit error rate are derived, and it is shown that their bounds are tight and the treated schemes can attain a given error rate with good throughput for moderately time-varying channels. Furthermore, the throughput is shown to be improved by the partial retransmission scheme compared with the whole retransmission scheme.

The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.

This paper describes the fabrication of 0.1 µm gate length CMOS devices and analysis of delay time by circuit simulation. In order to reduce the gate resistance, TiN capped cobalt salicide technology is applied to the fabrication of 0.1 µm CMOS devices. Gate sheet resistance with a 0.1 µm gate is as low as 5 Ω/sq. Propagation delay times of 0.1 µm and 0.15 µm CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15 µm, intrinsic delay in CMOS devices is the main dalay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1 µm, each parasitic component and intrinsic delay have similar contributions on device speed due to the short channel effect. To improve delay time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times and simulation predicted a delay time of 28 ps is possible with 0.15 µm CMOS inverters.

We have done a computer search for solutions of the equation x3y3z3n in the range max (|x|, |y|, |z|) 3414387 and 0 n 1000. We have discovered 21 new integer solutions for n {39, 143, 180, 231, 312, 321, 367, 439, 462, 516, 542, 556, 660, 663, 754, 777, 870}. As a result, there are 52 values of n (except n 4 (mod9)) for which no solutions are found.

We propose an asymmetric neural network which can solve inequality-constrained combinatorial optimization problems that are difficult to solve using symmetric neural networks. In this article, a knapsack problem that is one of such the problem is solved using the proposed network. Additionally, we study condition for obtaining a valid solution. In computer simulations, we show that the condition is correct and that the proposed network produces better solutions than the simple greedy algorithm.

In this paper, we propose a hybrid hierarchical global router for multi-layer VLSI's, which executes routing and layering simultaneously. This novel approach, a hybrid hierarchical global router, is a combination of a topdown and a bottomup hierarchical routers, and may be one of interesting routing techniques. We also show experimental results, which demonstrate the superiority of the hybrid hierarchical approach. This approach may have many possibilities to be used in a various fields.

This paper investigates the problem of scheduling parallel tasks" with consideration of communication cost on an m-processor system, where processors are assumed to be identical and tasks being scheduled are independent such that they can run on more than one processor simultaneously. Once a task is processed in parallel, its finish time will be speeded up, but communication cost will also be incurred and should be taken into account. To find a schedule with minimum finish time for the parallel tasks scheduling problem is NP-hard. Therefore, in this paper, we will propose a heuristic algorithm for this kind of problem and derive its performance bounds for two different cases of applications, respectively.

B-ISDN telecommunication systems will require signal processing speeds up to 600 Mbps or more. We must therefore consider the affects of signal reflection, signal attenuation, time dalay, and so on when designing these systems. The higher the signal speed, the larger the electrical noise induced around the connector, especially in the plated through holes (PTHs) area. This paper presents the results of our investigation focused on connector mounting configurations in the signal transmission line, especially whether or not signals transmit through the PTH in a printed circuit board (PCB). How the signal reflection characteristics depend upon transmission line configurations are discussed and experimental results and simulation analyses for a transmission line system using a small miniature A-type (SMA) connector as an example are performed. It is suggested that designs for future high-speed signal transmission circuits take into account the PTH diameter and/or the PTH pitch conditions, values for which can be determined from simulation analysis.

Telecommunication services are expected to be upgraded from POTS to B-ISDN services in the future. This means that the conventional metallic access networks should be upgraded to optical fiber access networks because of providing high bit-rate services. Therefore, it is very important to clarify upgrade strategies in access networks. This paper proposes a dynamic evaluation method that can support decision-making on the upgrade strategy from the viewpoint of economy. This method can determine the most promising future access network and upgrade timing. Moreover, viability of various upgrade strategies can be evaluated by this method.

There are various difficulties in processing spoken dialogs because of acoustic, phonetic, and grammatical ill-formedness, and because of interactions among participants. This paper describes temporal characteristics of utterances in human-human task-oriented dialogs and interactions between the participants, analyzed in relation to the topic structure of the dialog. We analyzed 12 task-oriented simulated dialogs of ASJ continuous speech corpus conducted by 13 different participants whose total length being 66 minutes. Speech data was segmented into utterance units each of which is a speech interval segmented by pauses. There were 3876 utterance units, and 38.9% of them were interjections, fillers, false starts and chiming utterances. Each dialog consisted of 6 to 15 topic segments in each of which participants exchange specific information of the task. Eighty-six out of 119 new topic segments started with interjectory utterances and filled pauses. It was found that the durations of turn-taking interjections and fillers including the preceding silent pause were significantly longer in topic boundaries than the other positions. The results indicate that the duration of interjection words and filled pauses is a sign of a topic shift in spoken dialogs. In natural conversations, participants' speaking modes change dynamically as the conversation develops. Response time of both client and agent role speakers became shorter as the dialog proceeded. This indicates that interactions between the participants become active as the dialog proceeds. Speech rate was also affected by the dialog structure. It was generally fast in the initiating and terminating parts where most utterances are of fixed expressions, and slow in topic segments of the body part of the dialog where both client and agent participants stalled to speak in order to retrieve task knowledge. The results can be utilized in man-machine dialog systems, e.g., in order to detect topic shifts of a dialog, and to make the speech interface of dialog systems more natural to a human participant.

We analyze all-optical switching property of a nonlinear directional coupler (NLDC) having an MQW coupling layer with both nonlinear and linear losses, and examine the effect of nonlinear losses. We use the Galerkin finite element method accompanied by a prodictor-corrector algorithm. The propagation loss along the strongly-coupled NLDC decreases with increasing nonlinear absorption coefficient due to saturation in absorption. A propagation loss of 8.18 dB or 2.38 dB in the bar state of the cross state is much smaller than the bulk loss of MQW structure which exceeds 50 dB. The nonlinear losses lengthen the coupling length and bring it close to that of a lossfree NLDC, while the linear losses shorten. It is found that the property of the cross state is greatly improved by counting the nonlinear losses: The cross-state output power and the output power ratio of two waveguides increase, and the cross state input power, that is, the switching power decreases.

We discuss properties of acyclic graph evolution driven by node-firing. The research background and basic concepts of acyclic graph evolution are from the mutual exclusion problem in distributed environments. We proposed in our previous work a mutual exclusion protocol which is based on the notion of evolution trajectories of acyclic graphs. In this paper, we analyze firing concurrency and periodicity of the acyclic graph evolution, from graph theoretical point of views, and investigate topological conditions for assuring the number of firable nodes below a some fixed constant, at any instance of the evolution trajectory. A marked graph, a subclass of Petri nets, is often utilized as a proof tool in analysis.

A novel delivery management system using a new lot sampling scheduling (LSS) method has been developed. The method involves the concepts of "virtual line" and "marker lot," and the system consists of an on-line scheduler executing short-period scheduling for lot-tracking and an off-line scheduler executing long-period scheduling for delivery date simulation. The LSS method can hugely increase the maximum number of lots to simulate the delivery date and also control TAT more effectively compared to conventional dynamic scheduling. Lot progress is controlled by varying the resource allocation ratio for each virtual line. This method is effective for precise delivery date control of lots with various priorities in ASIC production or development lines.

This paper presents a method for spatial and temporal segmentation of long image sequences which include multiple independently moving objects, based on the Minimum Description Length (MDL) principle. By obtaining an optimal motion description, we extract spatiotemporal (ST) segments in the image sequence, each of which consists of edge segments with similar motions. First, we construct a family of 2D motion models, each of which is completely determined by its specified set of equations. Then, based on these sets of equations we formulate the motion description length in a long sequence. The motion state of one object at one moment is determined by finding the model with shortest description length. Temporal segmentation is carried out when the motion state is found to have changed. At the same time, the spatial segmentation is globally optimized in such a way that the motion description of the entire scene reaches a minimum.

In this paper we propose a co-design method for control systems using combination of models. By co-design," we mean a cooperative design method in which the behavior of the entire system is simulated as a single model while parameters of the system are being optimized. Our co-design method enables the various subsystems in the system, which have been designed independently as tasks assigned to different designers in the traditional design method, to be designed simultaneously in a unified cooperative way from the system-wide perspective of a system designer. Our proposed method combines models of controlling and controlled subsystems into a single model for the behavior of the entire control system. After the optimum control conditions are determined through simulation of the combined models, based on the corresponding algorithms and parameters, ASIC design proceeds quickly with accurate verification using iterative replacements of the behavior model by the electronic circuit model. To evaluate the proposed method, we implemented a design environment. We then applied our method to the design of ASICs in three test cases (in a control system and in audio-visual systems) to investigate its effectiveness. This paper introduces the concepts of the proposed co-design method, the design environment and the experimental results, and points out the new issues for system design.

It has become more important to reduce the protocol implementation costs as the functions of protocols have become more abundant. The protocol implementation tools which automatically generate a protocol program from a specification described by an FDT (Formal Description Technique) are very promising. Selecting SDL as a target FDT, we have developed an SDL-based protocol implementation tool which consists of a process scheduler and a compiler. Since the efficient SDL process execution is a key to generating the high-speed program, the scheduler is introduced. It provides the mechanism which executes SDL processes concurrently as light-weight-processes. It optimizes so that as few context switches take places as possible. The compiler converts as many kinds of SDL functions whose behaviors can be determined at compile time into programming language statements as possible. These elaborations are so successful that the tool can generate an efficient program. The OSI Transport protocol class 0 program generated by the compiler can process more than 500 packets per second on a 6MIPS workstation.

In this report, we propose a robust block adaptive digital filter (BADF) which can improve the accuracy of the estimated weights by averaging the adaptive weight vectors. We show that the improvement of the estimated weights is independent of the input signal correlation.

This paper proposes a universal structure for STM-N(N=1, 2, 3, ) multiplex line terminals that only utilizes N chips CMOS LSIs for Section OverHead (SOH) processing. The uniquely configured LSIs are applicable to any STM-N line terminal equipment. Reasonable frame alignment performance attributes, such as the maximum average reframe time, false in-frame time, out-of-frame detection time, and misframe time, are calculated for the configuration. A prototype SOH processing LSI built on 0.8m BiCMOS technology successfully realizes the functions needed for multiplex section termination. The STM-64 frame is also demonstrated using the proposed circuit configuration and prototype LSIs.

0.15 µm CMOS transistors have been fabricated. TiSi2 salicide was used for the gate electrode and source/drain to reduce parasitic resistance. Electron beam (EB) lithography was used for the gate patterning. Since the channel impurity was implanted only around the gate to reduce the junction capacitance, a reasonably short ring oscillator delay of 33 ps was obtained at 1.9 V supply voltage. The parasitic resistance and capacitance contribution on the delay time was analyzed by SPICE simulation. It was shown that the localized channel implant is effective for scaling the delay time and power consumption, because the source/drain size difficult to scale down to as small as the gate length.