For a CBR (Constant Bit Rate) connection in an ATM (Asynchronous Transfer Mode) network, we determine the CDV (Cell Delay Variation) tolerance for the mapping of ATM cells from the ATM Layer onto the Physical Layer. Our result will be useful to properly allocate resources to connections and to accurately enforce the contract governing the user's cell traffic by UPC (Usage Parameter Control).

This paper proposes a new environment for high-level VLSI design specification validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples (a protocol processor, an 8-bit CPU, and a Prolog processor). A design is specified at a high-level using the structured analysis (SA) method, which is useful for analyzing and understanding the functionality to be realized. The specification written in SA is transformed into a logic programming language and is simulated in it. The errors (which terminate with an incorrect output in the simulation) included in the three large examples are efficiently located by answering junt a few queries from the algorithmic debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. The correct SA specification can be automatically translated into a Register Transfer Level (RTL) specification suitable for logic synthesis. In this environment, a designer is freed from the tedious task of debugging a RTL specification, and can concentrate on the design itself. This environment promises to be an important step towards efficient high-level VLSI design specification validation.

A multi-stage noise-shaping (MASH) A/D converter combining an RC-integrator and a digital correction technique for high accuracy is described. Using 1.2-µm BiCMOS technology, we developed an A/D converter for digital audio with an S/N ratio of over 100 dB. This paper discusses the principles of MASH technology with an RC-integrator, the technique for correcting RC variation, and the experimental results obtained with a fabricated chip.

Considering the trend towards adopting high efficiency picture coding schemes into digital broadcasting services, we investigate objective picture quality scales for evaluating digitally encoded still and moving pictures. First, the study on the objective picture quality scale for high definition still pictures coded by the JPEG scheme is summarized. This scale is derived from consideration of the following distortion factors; 1) weighted noise by the spatial frequency characteristics and masking effects of human vision, 2) block distortion, and 3) mosquito noise. Next, an objective picture quality scale for motion pictures of standard television coded by the hybrid DCT scheme is studied. In addition to the above distortion factors, the temporal frequency characteristics of vision are also considered. Furthermore, considering that all of these distortions vary over time in motion pictures, methods for determining a single objective picture quality value for this time varying distortion are examined. As a result, generally applicable objective picture quality scale is obtained that correlates extremely well with subjective picture quality scale for both still and motion pictures, irrespective of the contents of the pictures. Having an objective scale facilitates automated picture quality evaluation and control.

This paper presents an analysis of the control characteristics of the series resonant converter with a parallel resonant circuit, especially under parallel resonant frequency. Operations of the circuit are classified into several modes. The control characteristics are calculated using the equations derived from equivalent circuits, and are verified by the experiments. From the analysis, the mechanism of a jumping phenomenon in the closed-loop control characteristics is clarified.

This paper compares three typical system-sharing configurations for FTTH networks that provide narrowband and video distribution services and proposes a remote node locating strategy for each configuration. Two new evaluation factors, required land space and service provisioning effort, are included in the calculation, in addition to facility cost and maintenance effort. By considering these factors together, the total network cost is calculated and the sensitivity to the number of remote nodes is evaluated. Finally, the most economical system-sharing configuration is identified on the basis of the evaluations for two typical service areas in Japan, for both present and future cost environments.

This paper describes a new clustering approach for VLSI placement, which is based on a fractal dimension analysis for the topological structure of modules in a logic diagram. A distinctive feature of this approach is that a measure of the 'fractal dimension' has been introduced into a logic diagram in such a way that the clustering of modules is iterated while the fractal dimension among clustered modules is retained in a prescribed range. A part of experimental results is also shown, which demonstrates that our clustering approach raises the placement performance much higher than the conventional clustering methods.

This paper presents a new sort of multilayer piezoelectric ceramic transformer for switching regulated power supplies. This piezoelectric transformer operates in the second thickness extensional vibration mode. Its resonant frequency is higher than 1 MHz. First, numerical simulation was implemented using a distributed constant electromechanical equivalent circuit method. It was calculated that this piezoelectric transformer, which has higher than 200 mechanical quality factor Qm, could work with higher than 90% efficiency and in more than 20-W/cm3 high power density. Second, a trially fabricated transformer, which is 15 mm long, 15 mm wide and 2.2 mm thick, was examined. Modified PbTiO3 family ceramics were used for the piezoelectric transformer material, because of the large anisotropy between electromechanical coupling factors kt and kp. Obtained results indicate that the piezoelectric transformer has good resonant characteristics, with little spurious vibration, and exhibits 16-W/cm3 power density with high efficiency at 2 MHz. Moreover, a switching regulated power supply, applying the piezoelectric ceramic transformer, was built and examined.

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

This paper proposes a new signaling technique which employs multilevel block codes in conjunction with phase/frequency modulation. The proposed scheme exhibits an increased minimum squared Euclidean distances (MSEDs) and outperforms other conventional schemes in terms of asymptotic coding gain and decoding complexity. The proposed scheme is also considered for non-constant amplitudes, which turned out to show even better performances at small modulation indices in some cases. Examples are given to demonstrate how to optimize the signal set for a given block code to maximize the coding gain.

In this letter an SR-latch circuit using Hopfield neural networks is introduced. An energy function suited for a neural SR-latch circuit is defined for which the global convergence is guaranteed. We also demonstrate how to compose master-slave (M/S) SR- and JK-flip flops of novel SR-latch circuits, and further an asynchronous binary counter of M/S JK-flip flops. Computer simulations are included to illustrate how each presented circuit operates.

This paper presents a fast and practical routing algorithm implemented on a supercomputer. In previously reported work, routing has been accelerated by executing the maze algorithm on parallel processing elements. However, although many parallel algorithms and special architectures have been introduced, practical aspects have not been addressed. We therefore present a novel approach that uses a vector processor as a routing accelerator and a wavefront control algorithm in order to avoid the wasteful searches that often occur in industrial routing problems. Experimental results that show the performance of a supercomputer using these algorithms is equivalent to over 1800 VAXMIPS, the fastest yet reported for routing accelerators. Results with industrial data also prove the validity of our approach.

Mixed-signal LSIs promise to permit increased levels of integration, not only in voiceband but also in multi-GHz-band applications such as wireless communications and optical data links. This paper reviews the evolution of mixed-signal communications LSIs and discusses some of their design problems, including device noise and crosstalk noise. In the low-power and low-voltage designs emerging as new disciplines, the target supply voltage for voiceband LSIs is around 1 V, and even GHz-band circuits are approaching 2 V. MOS devices are expected to play an important role even in the frequency range over 100 MHz, in the area of wireless or optical communications circuits.

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.

This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.

The statistical properties of insertion losses and return losses for optical connectors are investigated theoretically using the probability theory and the Monte Carlo simulation. Our investigation is focused on an orientation method for reducing insertion loss by which a fiber-core center is adjusted in a region of within a certain angle to the positioning key direction. It is demonstrated that the method can significantly improve insertion losses, and that an adjusting operation angle of 90 degrees is sufficient to realize an insertion loss of less than 0.5 dB with 99% cumulative probability. Good agreement was obtained between the theoretical distribution and the experimental results for single-mode fiber connection. Consequently, it is indicated that the statistical distributions of insertion losses and return losses of optical connectors in the field can be predicted theoretically from the values measured in the factory by connection to a master connector.

Electromagnetic plane wave scattering by a loaded trough on a ground plane has been analyzed by Kobayashi and Nomura's method. The field in each region is expressed first in terms of appropriate eigen functions, whose excitation coefficients are determined by the continuity condition across the aperture of the trough. Simple far field expression which is suitable for numerical calculation for small aperture cases has been derived. Scattering far field patterns and radar cross section are calculated and compared with those obtained by other methods. Good agreements have been observed for all incident angles.

A novel effective channel length extraction method has been developed, which utilizes the difference between the local threshold voltage of channel region and that of external region. In this method, the dependence of external resistance on Vg is taken into account, and it is not necessary to extract Vth. It is found that the external resistance can be approximated as the linear function of Vg with Vg around Vth. For a 0.4 µm gate length LDD MOSFET, the accuracy and resolution are estimated to be less than 0.02 µm and 0.003 µm, respectively.

OFDM (Orthogonal Frequency Division Multiplexing) is a useful digital modulation method for terrestrial digital broadcasting systems, both for digital TV broadcasting and digital audio broadcasting. OFDM is a kind of multicarrier modulation and shows excellent performance especially in multipath environments and in mobile reception. Other advantages are its resistance to interference signals and its suitability for digital signal processing. When each carrier of the OFDM signal is modulated with DQPSK, we call it DQPSK-OFDM. DQPSK-OFDM is a basic OFDM system, which is especially suitable for mobile reception. This paper describes how a DQPSK-OFDM system works and shows several experimental and simulation results. The experimental results mainly concern the performance of the DQPSK-OFDM system relative to various disturbances such as multipath (ghost) signals, nonlinearity of the channel, and interference from analog signals. The transmission characteristics of DQPSK-OFDM are investigated and the basic criteria for the system design of DQPSK-OFDM are discussed.

We have developed a Virtual Playground," which allows various activities such as virtual playground and virtual visiting areas for hospitalized children who can not usually go outside. A Virtual Playground system is composed of TV monitors, joysticks, cameras, video transmission devices, and a graphics workstation. In a Virtual Playground environment, children can experience what is impossible or difficult during their stay in a hospital. We have completed a couple of experiments already and discussed its effects.* In our recent work, we also introduced a simple version of the Cave display to the Virtual Playground system.