A new bipolar scan waveform is proposed to increase the light emission duty factor by achieving the fast address in AC plasma display panel (AC-PDP). The new bipolar scan waveform consists of two-step scan pulse, which can separate the address discharge mode into two different discharge modes: a space charge generation mode and a wall charge accumulation mode. By adopting the new bipolar scan waveform, the light emission duty factor is increased considerably under the single scan ADS driving scheme due to the reduction of address time per single subfield.

The power dissipation at the off-chip bus has become a significant part of the overall power dissipation in micro-processor based digital systems. This paper presents irredundant address bus encoding methods which reduce signal transitions on the instruction address buses by using adaptive codebook methods. These methods are based on the temporal locality and spatial locality of instruction address. Since applications tend to JUMP/BRANCH to limited sets of addresses, proposed encoding methods assign the least signal transition codes to the addresses of JUMP/BRANCH operations in the past. In addition, our methods can be easily applicable for conventional digital systems since they are irredundant encoding methods. Our encoding methods reduce the signal transitions on the instruction address buses, which results in the reduction of total power dissipation of digital systems. Experimental results show that our methods can reduce the signal transition by an average of 88%.

Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.

A simple address indexing method is proposed for path memory management in multi-PE Viterbi decoder, which solves data read/write conflict problem completely. This method not only simplifies control and addressing overhead but also has the advantage of requiring only two memory banks regardless of the number of PE's, with 100% PE utilization.

Randomly addressed polling was proposed as a multiple access control protocol for wireless local area networks (LANs). However, the protocol has difficulties in supporting real-time services such as voice transmission. We propose a reservation scheme and make it possible to support real-time services. The scheme is described in detail. Efficiency and average access delay are analyzed.

This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-µm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.

This paper investigates the stochastic property of packet destinations in order to describe Internet access patterns. If we assume a sort of stationary condition for the address generation process, the process is an LRU stack model. Although the LRU stack model gives appropriate descriptions of address generation on a medium/long time-scale, address sequences generated from the LRU stack model do not reproduce Zipf-type distributions, which appear frequently in Internet access patterns. This implies that the address generation behavior on a short time-scale has a strong influence on the shape of the distributions that describe frequency of address appearances. This paper proposes an address generation algorithm that does not meet the stationary condition on the short time-scale, but restores it on the medium/long time-scale, and shows that the proposed algorithm reproduces Zipf-type distributions.

A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.

It is widely recognized that IP-based mobile network will be a dominant trend. For mobile IP networks, the address starvation problem and scalable mobility management for mobile nodes are important issues. In order to cope with these issues, we propose an approach to realize mobile IP network supporting private addresses for mobile nodes. Our approach introduces regional registration of mobile nodes (Hierarchical Mobile IPv4) and coordinates NAT and DNS functions with the Mobile IP protocol. It enables a mobile node to be assigned a global address temporally in a visited network and to accept a call initiated by a correspondent node connected to the global IP network. This paper describes the detailed design of our approach and the implementation of proposed procedures based on the Mobile IPv4 software developed by the CMU Monarch project.

A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.

Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.

This paper investigates the stochastic property of the packet destinations and proposes an address generation algorithm which is applicable for describing various Internet access patterns. We assume that a stochastic process of Internet access satisfies the stationary condition and derive the fundamental structure of the address generation algorithm. Pseudo IP-address sequence generated from our algorithm gives dependable cache performance and reproduces the results obtained from trace-driven simulation. The proposed algorithm is applicable not only to the destination IP address but also to the destination URLs of packets, and is useful for simulation studies of Internet performance, Web caching, DNS, and so on.

This paper proposes a managed IP multicast platform that enables IP multicast services to be used for business. Nowadays, many business applications have switched from traditional network platforms to the IP platform. Among these applications, one-to-many or many-to -many types of applications are especially essential to business users. These applications may use IP Multicasting for transmitting data to many users. However, for business applications, it is difficult to use the present IP Multicast services, because they lack many requirements for business usage. The requirements are address management, authentication, time management, and guaranteed throughput. To satisfy the business users, we made the design of a managed IP multicast platform that will meet these requirements. Our platform, which separates the routing control layer and the packet forwarding layer, is called GMN-CL (Connection Technologies for Global Mega-media Network). The routing control layer manages routing information and controls network routing centrally, so it can understand the whole network situation and perform efficient routing. The packet forwarding layer can concentrate completely on forwarding, so the forwarding speed and copying speed is higher than when using routers. We have implemented our design of a managed IP multicast platform over GMN-CL. This paper reports the system design, implementation, and evaluation.

In this paper, we proposed two models, the full multiple MCS (Multicast Server) model and the hybrid multiple MCS model to support multiple MCS over a single large cluster in ATM (Asynchronous Transfer Mode) networks. Also, we presented two methods for MCS assignment which are known as 2PSPMT (2 Phase Shortest Path based on Multicast tree) and hybrid-2PSPMT, and evaluated its performance by simulation. When an ATM host requests joining a specific multicast group, the MARS (Multicast Address Resolution Server) designates a proper MCS among the multiple MCSs for the group member to minimize the average path delay between the sender and the group members. Each method for MCS assignment construct a 2-phase partial multicast tree based on the shortest path algorithm. We reduced the average path delay in the multicast tree using these methods with various cluster topologies and MCS distribution scenarios in addition to distributing the load among multiple MCSs.

CAM (Content Addressable Memory) units are generally designed so that they can be applied to variety of application programs. However, if a particular application runs on CAM units, some functions in CAM units may be often used and other functions may never be used. We consider that appropriate design for CAM units is required depending on the requirements for a given application program. This paper proposes a CAM processor synthesis system based on behavioral descriptions. The input of the system is an application program written in C including CAM functions, and its output is hardware descriptions of a synthesized processor and a binary code executed on it. Since the system determines functions in CAM units and synthesizes a CAM processor depending on the requirements of an application program, we expect that a synthesized CAM processor can execute the application program with small processor area and delay. Experimental results demonstrate its efficiency and effectiveness.

The change over from IPv4 to IPv6 entails a potential increase in the number of records that the Registry System must maintain. Currently, only a few Network Information Centers (NICs), controlled by Internet Assigned Number Authority (IANA), operate their Registry Systems. As they concentrates data into several Registry System, it is not scalable. This paper focuses on the scalability issue in a Registry System and Mie Advanced Registry System (MARS) is proposed. Through the collaboration of independent Registry Systems, MARS ensures data consistency as well as making it possible to access data managed by other Registry Systems. A prototype system of MARS is implemented, maintained and managed on the WIDE 6bone. Some lessen from the operation of MARS give also described.

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called "switched diffusion analog memory with feedback circuit (FBSDAM). " FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4µm double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology.

In order to lessen overflow or underflow problem in numerical computation, several new floating-point arithmetics have been proposed. The significant advantage of these new arithmetics is that a number can be represented in a wider range since the fields of exponent and mantissa are changed depending on the magnitude of number. The main issues of these arithmetics are how to find the boundary between exponent and mantissa as well as to convert the formats between new floating-point arithmetic and fixed-point arithmetic quickly. In this paper, a CAM-based array converter based on the Universal Representation of Real number (URR) floating-point arithmetic is described. Using match retrieval device CAM, the detection of the boundary can be accomplished faster than conventional circuits. Arranging the basic cells into iterative array structure, the fast separation/connection operation is achieved. The speed, area and power consumption of the converter is estimated.

The new technique for reducing the load latency is presented. This technique, named tunneling-load, utilizes the register specifier buffer in order to reduce the load latency without fetching the data cache speculatively, and thus eliminates the drawback of any load address prediction techniques. As a consequence of the trend toward increasing clock frequency, the internal cache is no longer able to fill the speed gap between the processor and the external memory, and the data cache latency degrades the processor performance. In order to hide this latency, several techniques predicting the load address have been proposed. These techniques carry out the speculative data cache fetching, which causes the explosion of the memory traffic and the pollution of the data cache. The tunneling-load solves these problems. We have evaluated the effects of the tunneling-load, and found that in an in-order-issue superscalar platform the instruction level parallelism is increased by approximately 10%.

This paper proposes the Dual Zipfian Model addressing how to describe HTTP access trends in large-scale data communication networks, and discusses how to design the capacity of address cache tables in an edge router of the networks. We show that destination addresses of packets can be characterized by two types of Zipf's law. Fundamental concept of the Dual Zipfian Model is in complementary use of these laws, and we can derive the relationship between the number of accesses and the number of destination addresses. Experimental results show that the relation gives a good approximation. Applying this relation, we derive cache hit probabilities of the address cache table that incorporates high-speed address resolution. Using the probabilities, design issues including the capacity of the cache tables and aging algorithms of cache entries are also discussed.