In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.

To deal with the increasing number of mobile devices accessing the Internet and the increasing demands of mobility management, IETF has proposed Mobile IPv6 and its fast handover protocol FMIPv6. In FMIPv6, the possibility of Care-of Address (CoA) collision and the time for Return Routability (RR) procedure result in long handover delay, which makes it unsuitable for real-time applications. In this paper, we propose an improved handover scheme for FMIPv6, which reduces the handover delay by using proactive CoA acquisition, configuration and test method. In our proposal, collision-free CoA is proactively prepared, and the time for RR procedure does not contribute to the handover delay. Furthermore, we analyze our proposal's benefits and overhead tradeoff. The numerical results demonstrate that it outperforms the current schemes, such as FMIPv6 and enhanced FMIPv6, on the aspect of handover delay and packet transmission delay.

In this work, we propose a scheme of routing table compaction for IP forwarding engines based on ternary content addressable memory (TCAM). Our scheme transforms the original routing table into a form with only disjoint prefixes. The most prevalent next hop of the routing table is then calculated and the route prefixes corresponding to the next hop are replaced by one TCAM entry. In combination with Espresso-II logic minimization algorithm, the proposed scheme reduces the TCAM storage requirements by more than 75% compared to the original routing tables. We also present an effective approach to support incremental updates.

According to the recent observations of IPv4 (Internet Protocol version 4) address allocation status, it will be running out within few years. Consequently, to ensure the continuous extension of the Internet operation, introducing IPv6 (Internet Protocol version 6) protocol is surely needed. But at the same time, such transformation must be "smooth" for every Internet users and be compatible with today's IPv4 based practices. This paper describes several techniques and usage scenario which are discussed mainly in the IETF -- Internet Engineering Task Force -- and tried to be implemented as prototype products to transform today's Internet towards the IPv6 based one.

In this letter, a novel technique for fast block matching using a new matching criterion is proposed. The matching speed and image quality are controlled by the one control parameter called matching region ratio. An efficient matching scheme with a gradual voting strategy is also proposed. This scheme can greatly boost the matching speed. The proposed technique is fast and applicable even in the presence of speckle noise or partial occlusion.

This letter proposes a fast IP address lookup algorithm based on search space reduction. Prefixes are classified into three types according to the nesting relationship and a large forwarding table is partitioned into multiple small trees. As a result, the search space is reduced. The results of analyses and experiments show that the proposed method offers higher lookup and updating speeds along with reduced memory requirements.

The current Internet is not capable of meeting the future communication requirements of society, i.e., reliable connectivity in a ubiquitous networking environment. The shortcomings of the Internet are due to the lack of support for mobility, multihoming, security and heterogeneous network layer protocols in the original design. Therefore, to provide ubiquitous networking facilities to the society for future innovation, we have to redesign the future Internet, which we call the New Generation Network. In this paper, we present the Heterogeneity Inclusion and Mobility Adaptation through Locator ID Separation (HIMALIS) architecture for the New Generation Network. The HIMALIS architecture includes a new naming scheme for generating host names and IDs. It also includes a logical control network to store and distribute bindings between host names, IDs, locators and other information useful for providing support for network operation and control. The architecture uses such information to manage network dynamism (i.e., mobility, multihoming) and heterogeneity in network layer protocols. We verify the basic functions of the architecture by implementing and testing them using a testbed system.

To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time by using the Vt closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of Vscanw, was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of Vscanw, also.

This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.

Recently, Kempf and Koodli have proposed a security protocol for Fast Mobile IPv6 (FMIPv6). Through the SEcure Neighbor Discovery (SEND) protocol, it achieves secure distribution of a handover key, and consequently becomes a security standard for FMIPv6. However, it is still vulnerable to redirection attacks. In addition, due to the SEND protocol, it suffers from denial of service attacks and expensive computational cost. In this paper, we present a security protocol, which enhances Kempf-Koodli's one with the help of the AAA infrastructure.

This paper presents two power-saving designs for Quadratic Polynomial Permutation (QPP) interleave address generator of which interleave length K is fixed and unfixed, respectively. These designs are based on our observation that the quadratic term f2x2%K of f(x) = (f1x+f2x2)%K, which is the QPP address generating function, has a short period and is symmetric within the period. Power consumption is reduced by 27.4% in the design with fixed-K and 5.4% in the design with unfixed-K on the average for various values of K, when compared with existing designs.

Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.

This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.

IPv4 private addresses are commonly used in local area networks (LANs). With the increasing popularity of virtual private networks (VPNs), it has become common that a user connects to multiple LANs at the same time. However, private address ranges for LANs frequently overlap. In such cases, existing systems do not allow the user to access the resources on all LANs at the same time. In this paper, we propose name-based address mapping for VPNs, a novel method that allows connecting to hosts through multiple VPNs at the same time, even when the address ranges of the VPNs overlap. In name-based address mapping, rather than using the IP addresses used on the LANs (the real addresses), we assign a unique virtual address to each remote host based on its domain name. The local host uses the virtual addresses to communicate with remote hosts. We have implemented name-based address mapping for layer 3 OpenVPN connections on Linux and measured its performance. The communication overhead of our system is less than 1.5% for throughput and less than 0.2 ms for each name resolution.

Most routing protocols in MANET use IP addresses as one of the most important routing information. To implement the routing protocol of MANET, the IP assignment in MANET should be solved. Allocating IP addresses is one of current key issues in the MANET, due to the absence of a centralized agent server. Previous methods require a large address space or can not use all the IP addresses of the given IP address space. For that reason, many IP addresses remain unused. To resolve this, we propose an IP address assignment protocol that uses the contiguous IP address assignment strategy without unused IP addresses. Simulations perform on ns-2 and confirm the viability of our protocol.

In this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the frame buffer and each line stores an 8 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.

This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.

This letter presents a race-free mixed serial-parallel comparison (RFMSPC) scheme which uses both serial and parallel CAMs in a match line. A self-reset search line scheme for the serial CAM is proposed to avoid the timing race problem and additional timing penalties. Various 32 entry CAMs are designed using 90 nm 1.2 V CMOS process to verify the proposed RFMSPC scheme. It shows that the RFMSPC saves power consumption by 40%, 53% and 63% at the cost of a 4%, 6% and 16% increase in search time according to 1, 2, and 4 serial CAM bits in a match line.

This paper proposes a new reset driving waveform to widen the driving margin under a low address voltage in AC-PDPs. The proposed reset waveform alters the wall charge distribution between the X-Y electrodes by applying an X-ramp bias prior to an address-period, thereby lowering the minimum level of the scan pulse (ΔVy) during an address-period without any misfiring discharge in the off-cells. When adopting the proposed reset waveform, the address discharge time delay is reduced by about 200 ns at an address voltage of 35 V, while the related dynamic driving margin is wide under a low address voltage condition. The related phenomena are also examined using the Vt close-curve method.