We propose a new label recognition system for photonic label switching using self-routing of labels. Binary-coded labels in on-off keying format are considered. The system consists of an all-optical demultiplexer (DeMUX) and an address recognition unit (ARU) consisting of tree-structured switches. The system uses self-routing propagation of an indication bit controlled with address bits. The indication bit is placed in advance of the address bits in the label. In DeMUX, all-optical switches in a configuration of Mach-Zehnder interferometer with semiconductor optical amplifiers (SOA-MZI) are controlled by the indication bit pulse to separate each of the label bits. The indication bit pulse is routed to the destination output port corresponding to the code of the address in ARU. It is shown that all the binary number codes can be recognized with this system. The operation principle is verified by numerical simulation using coupled-mode theory and a rate equation. Moreover, the switching crosstalk is also evaluated.

Multicast delivery in heterogeneous wireless networks requires careful coordination, in order to take full advantage of the resources such an interworking network environment can offer. Effective coordination, however, may require interworking signaling from coordinating network entities to receivers of a multicast service. Scalable delivery of such signaling is of great importance, since a large number of receivers may be interested in a multicast service. This paper therefore investigates the use of a multicast signaling channel (MSCH) to carry such interworking signaling in a scalable manner. Applications of interworking signaling for multicast service delivery in heterogeneous wireless networks are presented, motivating the need for an MSCH. Then a comparative study is performed analysing potential benefits of employing an MSCH for signaling message delivery compared to conventional unicast signaling. The analysis reveals that the benefits of the MSCH depend mainly on the selection of an appropriate signaling network to carry the MSCH and also on efficient addressing of a subset of receivers within the MSCH. Based on the findings, guidelines for the selection of a suitable signaling network are provided. Furthermore a novel approach is proposed that allows efficient addressing of a subset of receivers within a multicast group. The approach minimizes the required signaling load on the MSCH by reducing the size of the required addressing information. This is achieved by an aggregation of receivers with common context information. To demonstrate the concept, a prototype of the MSCH has been developed and is presented in the paper.

This paper investigates fast Packet Classification techniques, where a large routing table is divided into many much smaller tables by an index key at first; the resulting small tables are much easier to search. A traditional way is to use the front bits as the index key, but we show it's not an effective way to divide a routing table. In this paper, we propose three bit selection methods for division. They can be implemented by CAM or hash structure. Simulations show that the bit selection methods decrease the delay of classification 50% compared to the traditional method. We also propose an optimized method which is adapted to the biased traffic pattern, which shows 70% improvement in our simulation.

This paper presents a novel optimized real-time Huffman encoder using a pipelined data path based on CAM technology and a parallel code-word-table optimizer. The exploitation of CAM technology enables fast parallel search of the code word table. At the same time, the code word table is optimized according to the frequency of received input symbols and is up-dated in real-time. Since these two functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. Evaluation results for the JPEG application show that the proposed architecture can achieve up to 28% smaller encoded picture sizes than the conventional architectures. The obtained encoding time can be reduced by 95% in comparison to a conventional SRAM-based architecture, which is suitable even for the latest end-user-devices requiring fast frame-rates. Furthermore, the proposed architecture provides the only encoder that can simultaneously realize small compressed data size and fast processing speed.

This paper presents a scalable FPGA/ASIC implementation architecture for high-speed parallel table-lookup-coding using multi-ported content addressable memory, aiming at facilitating effective table-lookup-coding solutions. The multi-ported CAM adopts a Flexible Multi-ported Content Addressable Memory (FMCAM) technology, which represents an effective parallel processing architecture and was previously reported in [1]. To achieve a high-speed parallel table-lookup-coding solution, FMCAM is improved by additional schemes for a single search mode and counting value setting mode, so that it permits fast parallel table-lookup-coding operations. Evaluation results for Huffman encoding within the JPEG application show that a synthesized semi-custom ASIC implementation of the proposed architecture can already reduce the required clock-cycle number by 93% in comparison to a conventional DSP. Furthermore, the performance per area unit, measured in MOPS/mm2, can be improved by a factor of 3.8 in comparison to parallel operated DSPs. Consequently, the proposed architecture is very suitable for FPGA/ASIC implementation, and is a promising solution for small area integrated realization of real-time table-lookup-coding applications.

Recently, the number of multi-homed hosts is getting large, which are equipped with multiple network interfaces to support multiple IP addresses. Although there are several proposals that aim at bandwidth aggregation for multi-homed hosts, few of them support mobility. This paper proposes a new framework called AMS: Aggregate-bandwidth Multi-homing Support. AMS provides functions of not only bandwidth aggregation but also mobility by responding to the changes of the number of connections during communication without the support of underlying infrastructure. To achieve efficient data transmission, AMS introduces a function called address pairs selection to select an optimal combination of addresses of the peer nodes. We implemented AMS in the kernel of NetBSD and evaluated it in our test network, in which dummynet was used to control bandwidth and delay. The measured results showed that AMS achieved ideal bandwidth aggregation in three TCP connections by selecting optimal address pairs.

A high-speed drive technique is introduced in which addressing is done by eliminating, instead of accumulating, the wall charges. In the proposed scheme, wall charges are accumulated in all the cells in advance, and then the address discharges take place in selected cells to eliminate the wall charges. Sustain discharges are generated in these cells. In order to realize the proposed address scheme, re-designing of a setup waveforms was necessary. The data pulse of 1.33 µs wide and 84 V was realized in a Ne+10%Xe PDP. A contrast of 3,600:1 was obtained by providing one setup period in a TV field.

Secure communication in Mobile Ad Hoc Networks (MANETs) is important as nodes communicate over the wireless medium, which can be easily eavesdropped. Currently, the literature of secure IP address autoconfiguration in MANETs is extremely rare. In this paper, we propose five protocols that provide both secure IP address autoconfiguration and authenticated group key agreement (GKA) to give a more efficient and secure solution for MANET communications. Whenever a dynamic group membership event such as node join, node leave, network merge and network partition occurs, our protocols ensure that the IP address allocation table and group key are updated so that there are no address conflicts and leaving and joining users cannot decrypt future and previous communications respectively. A complexity analysis shows that despite having additional capabilities such as IP address autoconfiguration and key authentication, our protocols are still efficient when compared to other GKA protocols.

In this paper, we propose a new method to enhance the fault-tolerance of the Content Addressable Network (CAN), which is known as a typical pure P2P system based on the notion of Distributed Hash Table (DHT). The basic idea of the proposed method is to introduce redundancy to the management of index information distributed over the nodes in the given P2P network, by allowing each index to be assigned to several nodes, which was restricted to be one in the original CAN system. To keep the consistency among several copies of indices, we propose an efficient synchronization scheme based on the notion of labels assigned to each copy in a distinct manner. The performance of the proposed scheme is evaluated by simulation. The result of simulations indicates that the proposed scheme significantly enhances the fault-tolerance of the CAN system.

In this letter, a new addressing scheme for hexagonal networks is proposed. Using the new addressing scheme, many routing algorithms designed for networks using square-based topologies such as mesh and torus can also be applied to hexagonal networks. Methods of applying the turn model to hexagonal networks are derived, with some new minimal and partial adaptive routing algorithms obtained. Simulations of the new routing algorithms under different working conditions are carried on hexagonal networks of various sizes. The results show that the proposed algorithms can offer lower packet delay and loss rate than the popular dimension order routing algorithm.

Content-Addressable Network (CAN) provides a mechanism that could retrieve objects in a P2P network by maintaining indices to those objects in a fully decentralized manner. In the CAN system, index caching is a useful technique for reducing the response time of retrieving objects. The key points of effective caching techniques are to improve cache hit ratio by actively sharing caches distributed over the P2P network with every node and to reduce a maintenance and/or routing overhead for locating the cache of a requested index. In this paper, we propose a new caching technique based on the notion of proxy-type caching techniques which have been widely used in WWW systems. It can achieve active cache sharing by incorporating the concept of proxy caching into the index access mechanism and locate a closer proxy cache of a requested index with a little routing overhead. By the result of simulations, we conclude that it can improve the response time of retrieving indices by 30% compared with conventional caching techniques.

To achieve profits derived from multihoming, policy routing is supposed to be necessary. For routers' policy routing, some systems and implementations already exist. In addition to routers' operating systems with policy routing functions, IP Filter and iproute2 are useful for policy routing on routers. But they don't suit for policy routing on multihomed end-hosts because of differences on network environments between routers and end-hosts. In contrast with routers' network environments, there are some dynamic changes of network environments with some types of end-hosts, for example, laptop computers. Therefore, another policy routing system is needed for end-hosts' policy routing, which adapts to dynamic changes of network environment. PMPATH (Policy based MultiPATH routing system) is a policy routing system and designed especially for end-hosts uses. PMPATH uses source address selection as network selection, PMPATH can adapt to dynamic changes of network environment. PMPATH's policies for source address selection are defined in form of address block. PMPATH also provides outgoing interface selection. We implemented PMPATH on NetBSD 2.99.15 and tested its performance on multihomed end-hosts. PMPATH implementation works well even if there are changes of network environment. In this result, it is shown that PMPATH is useful for multihomed end-hosts' policy routing.

NAT-PT and DSTM are becoming more widespread as de-facto standards for IPv6 dominant network deployment. But few researchers have empirically evaluated their performance aspects. In this paper, we compared the performance of NAT-PT and DSTM with IPv4-only and IPv6-only networks on user applications using metrics such as throughput, CPU utilization, round-trip time, and connect/request/response transaction rate.

The XTR public key cryptosystem was introduced in 2000. XTR is suitable for a variety of environments including low-end smart cards, and is regarded as an excellent alternative to RSA and ECC. Moreover, it is remarked that XTR single exponentiation (XTR-SE) is less susceptible than usual exponentiation routines to environmental attacks such as the timing attack and the differential power analysis (DPA). This paper investigates the security of side channel attack (SCA) on XTR. In this paper, we show the immunity of XTR-SE against the simple power analysis if the order of the computation of XTR-SE is carefully considered. In addition, we show that XTR-SE is vulnerable to the data-bit DPA, the address-bit DPA, the doubling attack, the modified refined power analysis, and the modified zero-value attack. Moreover, we propose some countermeasures against these attacks. We also show experimental results of the efficiency of the countermeasures. From our implementation results, if we compare XTR with ECC with countermeasures against "SCAs," we think XTR is as suitable to smart cards as ECC.

A memory address allocation method for digital signal processors of indirect addressing with indexed auto-modification is proposed. At first, address auto-modification amounts for a given program are analyzed. And then, address allocation of program variables are moved and shifted so that both indexed and simple auto-modifications are effectively exploited. For further reduction in overhead codes, a memory address allocation method coupled with computational reordering is proposed. The proposed methods are applied to the existing compiler, and generated codes prove their effectiveness.

An event-driven sensor network composed of a large number of sensor nodes has been widely studied. A sensor node sends packets to a sink when the node detects an event. For the sink to receive packets it fails to acquire, the sink must send re-transmission requests to the sensor node. To send the requests to the sensor node using unicast, the network address of the sensor node is required to distinguish the sensor node from others. Since it is difficult to allocate the address manually to a number of nodes, a reasonable option is to use existing address autoconfiguration methods. However, the methods waste the limited energy of the sensor nodes due to using a number of control messages to allocate a permanent address to every node. In this paper, we propose an energy-efficient address autoconfiguration method for the event-driven sensor network. The proposed method allocates a temporary address only to a sensor node which detects an event, on an on-demand basis. By performing simulation studies, we evaluated the proposed method and compared it with one of the existing methods based on the number of control messages for the address allocation. The results show that the number of control messages of the proposed method is small compared to that of the existing method. We also evaluated the process time overhead of the proposed method using the implemented system. Although the proposed method has little extra overhead, the results show the processing time is short enough for practical use.

In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.

We propose an efficient IP address assignment protocol in mobile ad hoc networks, which use a proactive routing protocol. In this method, which is termed the Bisected-Range based Assignment (BRA), a node repeatedly broadcasts an Agent Request to ask for address assignment. If there are one or more neighbor MANET nodes, one of them becomes an agent to select and assign an IP address to the requesting node. We use address location in the IP address space so that each agent maintains its own exclusive address range to be used for address selection, resulting to decrease the possibility of address conflict. If the requesting node cannot discover any neighbor MANET node over pre-determined random agent-search time, it selects by itself an IP address at random from the given address block. We evaluate performance of the basic and enhanced BRAs by computer simulation. It is shown that the basic and enhanced BRAs can reduce address conflict compared with random assignment. It is also shown that the enhanced BRA is superior in terms of control traffic overhead as well as address assignment delay over the random assignment with the strong Duplicate Address Detection.

Most of system-on-chips (SOCs) have many memory cores. Diagnosis is often used to improve the yield of memories. Memory cores usually represent a significant portion of the chip area and dominate the yield of the chip. Memory diagnosis thus is one of key techniques for improving the yield and quality of SOCs. Content addressable memories (CAMs) are important components in many SOCs. In this paper we propose a three-phase diagnosis procedure for binary CAMs (BCAMs). The user can distinguish different types of BCAM-specific comparison and RAM faults and locate the faulty cells with the procedure. A March-like fault identification algorithm is also proposed. The algorithm can distinguish different types of faults--including typical RAM faults and BCAM-specific comparison faults. The algorithm requires 15N Read/Write operations and 2(N + B) Compare operations for an N B-bit BCAM. Analysis results show that the algorithm has 100% diagnostic resolution for the target faults.

In this paper, we focus on how to correct address mapping violation, in which an attacker rewrites the address mapping table of a victim to perform a Man-in-the-Middle (MITM) attack. We propose a technique for preventing MITM attacks in which a malicious user intercepts and possibly alters the data transmitted between two hosts. MITM attack is hard for legitimate users to notice during their normal communication, because each user believes they are communicating directly. Address mapping violation can occur because of vulnerability of address resolution protocols, Address Resolution Protocol (ARP) in IPv4 and Neighbor Discovery (ND) protocol in IPv6. Accordingly, a good method to prevent MITM attack by address mapping violation is essential for both current and future communications, i.e. wireless networks with roaming users and an interconnected world. Hence, our proposal mainly aims to have high usability in future applications such as embedded devices.