256 MbDRAM chips have been fabricated by mix-and-match method using high NA KrF excimer laser stepper and i-line stepper. In the case of KrF stepper, the negative siloxane resist is used for rectangular and wiring patterns and the positive novolak-resin resist is used for hole patterns. Both of these two kinds of resist produce accurate pattern shape, allow-able pattern profile, satisfactory depth of focus and sufficient overlay accuracy for device fabrication in 0.25 µm design rule.

The advantages of a neuro-chip architecture based on a DRAM are demonstrated through a discussion of the general issuse regarding a memory based neuro-chip architecture and a comparison with a chip based on an SRAM. The performance of both chips is compared assuming digital operation, a 1.5-V supply voltage, a 106-synapse neural network capability, and a 0.5-µm CMOS design rule. The use of a one-transistor DRAM cell array for the storage of synapse weights results in a chip 55% smaller than an SRAM based chip with the same 8-Mbit memory capacity and the same number of processing elements. No additional operations for refreshing the DRAM cell array are necessary during the processing of the neural networks. This is because all the synapse weights in the array are transferred to the processing elements during the processing and the DRAM cells in the array are automatically refreshed when they are selected. The precharge operation of the DRAM cell array degrades the processing speed, however a processing speed of 1.37 GCPS is expected for the DRAM based chip. That speed is comparable to the 1.71 GCPS for the SRAM based chip with the same 256 parallel-processing elements. A DRAM cell array has the additional advantage of lower power dissipation in this specific usage for the neuro-chip. The dynamic operation of the DRAM cell array results in a 10% lower operating power dissipation than a chip using an SRAM cell array at the same processing speed of 1.37 GCPS. That lower operating power dissipation enables a DRAM based chip to run on a 1.5-V dry cell for longer under intermittent daily use even though the SRAM cell array has little power dissipation in data-holding mode.

The goal of visual telecommunication has been to create a sense of "being there" or "telepresence." This paper introduces a novel shared drawing medium called ClearBoard that goes beyond "being there" by providing virtual shared workspace. It realizes (1) a seamless integration of shared drawing space and partner's image, and (2) eye contact to support real-time and remote collaboration by two users. We devised the key metaphor: "talking through and drawing on a transparent glass window" to design ClearBoard. A prototype, ClearBoard-1 is implemented based on the "Drafter-Mirror" architecture. This paper first reviews previous work on shared drawing support to clarify our design goals. We then examine three metaphors that fulfill these goals. The design requirements and the two possible system architectures of ClearBoard are described. Finally, some findings gained through the experimental use of the prototype, including the feature of "gaze awareness," are discussed.

Novel circuit design techniques for bipolar and MOS four-quadrant analog multipliers operable on low supply voltage are described. There are three design techniques for multipliers operable on low supply voltage. One is the transistor-size unbalance technique. Another is the bias offset technique. A third is the multitail technique. Bipolar and MOS four-quadrant analog multipliers proposed in this paper consist of transistor-pairs with different transistor sizes (i.e. emitter areas or gate W/L values are different), transistor-pairs with the same bias offset or multitail cells (i.e. quadritail cells and an octotail cell). Several kinds of squaring circuits consisting of such transistor-pairs are applied to the multipliers when the multiplication method is based on the quarter-square technique. These multipliers all have satisfiable multiplication characteristics with four-quadrant operations in analog signal processing, whether implemented in bipolar technology or implemented in MOS technology.

A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a capacitor contact between bit-lines. This memory cell enables usable capacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area is twice that of ordinary poly-silicon, was utilized for the storage node to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 µm2 memory cell with 30 fF storage capacitance using a 7 nm-SiO2-equivalent dielectric film and a 0.5 µm-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 µm CMOS process.

The concentration of the electric field at the edge of the electrode has been simulated in several types of flat DRAM cell capacitors with high permittivity dielectrics. The results indicated that the permittivity of the material surrounding the edge of the electrode as well as the geometrical structure affected the concentration of the electric field. The electric field strength was minimized and most evenly distributed by utilizing the structure in which the sidewall of the capacitor dielectric was terminated at the edge of the electrode by a low-dielectric constant insulator. High-precision fabrication of the capacitor's profile is required for the minimization and uniformity of the electric field.

We define the communication complexity of a perfect zero-knowledge interactive proof (ZKIP) as the expected number of bits communicated to achieve the given error probabilities (of both the completeness and the soundness). While the round complexity of ZKIPs has been studied greatly, no progress has been made for the communication complexity of those. This paper shows a perfect ZKIP whose communication complexity is 11/12 of that of the standard perfect ZKIP for a specific class of Quadratic Residuosity.

This paper describes a novel Recessed Stacked Capacitor (RSTC) structure for 256 Mbit DRAMs, which can realize the requirements for both fine-pattern delineation with limited depth of focus and high cell capacitance. New technologies involved are the RSTC process, 0.25 µm phase-shift lithography and CVD-tungsten plate technology. An experimental memory array has been fabricated with the above technologies and 25 fF/cell capacitance is obtained for the first time in a 0.61.2 µm2 (0.72 µm2) cell.

To improve the stability and the power supply rejection ratio (PSRR) of the voltage limiter circuit used in high-density DRAM's we present a voltage limiter circuit with pole-zero compensation. Analytical expressions that describe the stability of the circuit are provided for comprehensive consideration of circuit design. Voltage limiters with pole-zero compensation are shown to have excellent performance with respect to the stability, PSRR, and circuit area occupation. The parasitic resistances in internal voltage supply lines, signal transmission lines, and transistors are important parameters determining the stability of pole-zero compensation. Evaluation of a 16-Mbit test device revealed internal voltage fluctuations of 6% during operation of a chip-internal circuit, a phase margin of 53, and a PSRR of 30 dB.

If a perspective of the "256M/1G era" were to be made from this present, namely the last stage of the development of 64 M DRAMs, the process technologies will show a variety of progress. Some of them would remain only in the extension of the present ones, but others would show a fundamental change including their technological constitutions. The optical lithography will survive even the "256M/1G era" mainly with the innovations of mask technologies. The etching technologies will remain basically the same as the present ones, but will be much more refined. The studies on plasma/redical related surface reactions, however, will bring a variety of surface treatment technologies of new function. The interconnection technologies will encounter various kinds of difficulties both in materials and in processign, and mechanical processing will become one of ULSI processing technologies. The shallow junction technology will merge with the metallization and epitaxial growth technology. The thin dielectrics will approach a critical situation, and it might enhance the device structural change to three dimensional ones. Corresponding to this, the necessity of "vertical processing" will become larger. The bonding SOI technology might overcome these situations of increasing difficulties. On the other hand, the contamination control will be the base of these technology innovations and improvements, exploring a new technology field in addition to the conventional process technology fields.

GaAs MESFETs with a p-buffer layer (or a buried p-layer) are important devices for high-speed GaAs ICs. To study what conditions are required as a good substrate for ICs, we have investigated, by two-dimensional simulation, small-signal parameters and drain-current transients of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate. It is shown that the introduction of a p-buffer layer is effective to improve the transconductance and the cuttoff frequeycy. These parameters are not degrade even if the p-layer doping is increased and a neurtral p-region exists. It is also shown that drain-current drifts and hysteresis in I-V curves can occur in a case with a p-buffer layer, too. It is concluded that the introduction of a relatively highly-doped p-layer on a substrate with low acceptor and electron trap (EL2) densities is effective to realize the stable and high performance of GaAs MESFETs.

An effective bitline technique for high density DRAMs is studies. The open-type bitline structure where the bitlines are activated alternately can decrease the bitline noises and the current dissipation in memory cell arrays. In spite of several disadvantages inherent to the open-type bitline structure, this technique is found to get the larger read-out signal than the conventional bitline configurations for the DRAMs of 64 Mb and beyond. The effectiveness is confirmed with the measurement of the test-chips. This technique is expected to be more efficient for DRAMs of higher density, where the contribution of the inter-bitline capacitance is increased.

Logarithmic number systems (LNS) provide a very fast computational method. Their exceptional speed has been demonstrated in signal processing and then in computer graphics. But the precision problem of LNS in computer graphics has not been fully examined. In this paper analysis is made for the problem of LNS in picture generation, in particular for circle drawing. Theoretical error analysis is made for the circle drawing. That is, some expressions are developed for the relative error variances. Then they are examined by simulation experiments. Some comparisons are also done with floating point arithmetic with equivalent word length and dynamic range. The results show that the theory and the experiments agree reasonably well and that the logarithmic arithmetic is superior to or at least comparable to the corresponding floating point arithmetic with equivalent word length and dynamic range. Those results are also verified by visual inspections of actually drawn circles. It also shows that the conversion error (from integer to LNS), which is inherent in computer graphics with LNS, does not make too much influence on the total computational error for circle drawing. But it shows that the square-rooting makes the larger influence.

An extremely accurate and very wide-band quadrature modulator IC fabricated on a single chip using bipolar technology is presented. The characteristics of this quadrature modulator IC are much superior to conventional ones (modulation phase error and deviation from quadrature is about 1/10), and this IC is applicable to high modulation schemes such as 256 QAM. In this circuit, the phase difference between local signals input to each of two balanced modulators is detected by a phase detector, and a variable phase shifter in the local port is controlled automatically by the detected signals. This, along with the use of a wide-band variable phase shifter, enables the phase difference between the local signals input to the balanced modulators to be adaptively controlled to 90 degrees in wide frequency bands. In addition, a design method for the balanced modulators to obtain small modulation phase error is described. Based on this design method, a highly accurate quadrature modulator IC was fabricated, in which two balanced modulators, the phase detector, and the variable phase shifter were integrated on a single chip. Phase deviation from quadrature in the local signals was reduced to less than 0.3 degrees in the wide frequency bands of more tham 60 MHz. The modulation phase error of the balanced modulators wes less than 0.2 degrees at 140 MHz, and less than 2.5 degrees at up to 1.3 GHz.