We have applied hot-carrier circuit-level simulation to memory peripheral circuits of a few thousand to over 12K transistors using a simple but accurate degradation model for reliability verification of actual memory products. By applying simulation to entire circuits, it was found that the location of maximum degradation depended greatly upon circuit configuration and device technology. A design curve has been developed to quickly relate device-level DC lifetime to circuit-level performance lifetime. Using these results in conjunction with a methodology that has been developed to predict hot-carrier degradation early in the design cycle before TEG fabrication, accurate total-circuit simulation is applied early in the design process, making reliability simulation a crucial design tool rather than a verification tool as technology advances into the deep sub-micron high clock rate regime.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.

An extension is made for a set of systems that have a quadratic Lyapunov function in common for the purpose of analysis and design. The nominal set of system matrices comprises stable symmetric matricies, which admit a hyperspherical Lyapunov function. Based on stability robustness results, sets of matrices are constructed so that they share the same Lyapunov function with the nominal ones.

SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

We propose an interactive identification scheme based on the quadratic residue problem. Prover's identity can be proved without revealing his secret information with only one accreditation. The proposed scheme requires few computations in the verification process, and a small amount of memory to store the secret information, A digital signature based on this scheme is proposed, and its validity is then proved. Lastly, analysis about the proposed scheme is presented at the end of the paper.

A noble blind equalization algorithm (BEA) using a single/multilevel modulus is proposed. According to the residual intersymbol interference (ISI) level of the equalizer output, the new algorithm adopts relevantly a single modulus or a multilevel modulus to form its cost function. Moreover, since the proposed approach separates complex two-dimensional signal into in-phase and quadrature components, and forms the error signals for each component, it has inherently the capability of phase recovery. Hence, it improves the performances of steady-state and recovers the phase rotation without any degradation of transient property. Simulation results confirm the effectiveness of the new approach.

We extend the Rabin cryptosystem to the Eisenstein and Gauss fields. Methods for constructing the complete representation class and modulo operation of the ideal are presented. Based on these, we describe the methods of encryption and decryption. This proposed cryptosystem is shown to be as intractable as factorization, and recently presented low exponent attacks do not work against it.

The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.

This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.

The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.

A 2.7-V Si-bipolar quadrature modulator with a 90 phase shifter consisting of a frequency doubler and a master-slave flip-flop is described. The modulator operates over a wide bandwidth (0.95 to 1.88 GHz) without any tuning or adjustments. It is implemented using 20-GHz Si-bipolar technology and dissipates 97 mW at 2.7 V. An image ratio of less than -40 dBc is obtained between 1.1 and 1.8 GHz. Moreover, third-order harmonic products are less than -40 dBc and carrier leakage is less than -30 dBc.

This paper describes a novel quasi-transmission-line variable-reactance circuit that extends the variable-phase range of phase shifters. It consists of a transmission line and two shunt varactors. By appropriately choosing the characteristic impedance and electrical length of the transmission line, the variable-phase range can be significantly increased. Since the proposed circuit can be fabricated by the conventional MESFET process, a phase shifter can be integrated with other functional circuits. This enables fully monolithic integration of RF circuits as a one-chip multi-functional MMIC in radio communication systems. The variable-phase range of the prototype X-band monolithic phase shifter is 208 degrees, which is approximately four times as large as that of conventional one.

This paper presents the performance of a proposed GaAs MESFET photodetector with wide drain-to-gate distances for improving the optical coupling efficiency in subcarrier optical transmission. Principle and design parameters of the proposed MESFET are described. Link gain, CNR, and BER, are experimentally investigated as functions of the drain-to-gate distance. It is experimentally found that the proposed MESFET improves the link gain by 8.5 dB compared to the conventional structure at the subcarrier frequency of 140 MHz. Discussions are also included compared to PIN-PD.

This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.

We studied a 0.15-µm InGaP/InGaAs/GaAs pseudomorphic HEMT operating under a negative drain bias, using a parameter extraction technique based on an analytical parameter transformation. The bias-dependent data of smallsignal equivalent circuit elements was obtained from Sparameters measured at up to 62.5 GHz at various bias settings. We then described the intrinsic part of the device using a new empirical large-signal model in which charge conservation and dispersion effects were taken into consideration. As far as we know, this is the first report to clarify the behavior of a HEMT operating under negative drain bias. We included our largesignal model in a commercially-available harmonic-balance simulator as a user-defined model, and designed a 60 GHz MMIC oscillator. The fabricated oscillator's characteristics agreed well with the design calculations.

This paper proposes a fast timing recovery method with a decision feedback equalizer for baudrate sampling. The proposed method features two special techniques. The first one is for coarse estimation of the sampling phase. Internal signals of the oversampled analog-to-digital converter at different phases are directly taken out for parallel evaluation. The second technique provides fine tuning with a phase-modification stepsize which is adaptively controlled by the residual intersymbol interference. Simulation results by a full-duplex digital transmission system with a multilevel line code show superiority of the proposed method. The coarse timing estimation and the fine tuning reduce 75% and 40% of the time required by the conventional method,respectively. The overall saving in timing recovery is almost 60% over the conventional method. The proposed method could easily be extended to other applications with a decision feedback equalizer.

SOI DRAM's are candidates for giga-bit scale DRAM's due to the inherent features of SOI structure, and are also desired to be used as low-voltage memories which will be used in portable systems in the forthcoming multimedia era. However, some drawbacks are also anticipated owing to floating substrate effects. In this report, the advantages and problems concerning SOI DRAM's were reconsidered by evaluation of our test devices and also by analysis with device and circuit simulators for their future prospects. The following advantages of SOI DRAM's were verified. Low-voltage operation, active current reduction and speed gain were obtained by the reduced junction capacitance and the back-gate-bias effect. Static refresh characteristics were improved due to the reduced junction area. Soft error immunity was improved greatly by the complete isolation of the active region when the body potential is fixed. The problems that need to be resolved are closely related to the floating substrate effect. The soft error immunity in a floating body condition and the dynamic refresh characteristics were degraded by the instability of the floating body potential. Process and device approaches such as the field-shield-body-fixing method as well as circuit approaches like the BSG scheme are required to eliminate the floating substrate effects. From these investigations it can be said that a low-voltage DRAM with a current design rule would be possible if we pay close attention to the floating-substrate-related issues by optimizing various process/device and circuit techniques. With further development of the technology to suppress the floating substrate effects, it will be possible to develop simple and low-cost giga-bit level SOI DRAM's which use the SOI's inherent features to the full.