We present a method of extracting the digital inphase (I) and quadrature (Q) components from oversampled bandpass signals using narrow-band bandpass Hilbert transformers. Down-conversion of the digitized IF signals to baseband and reduction of the quantization noise are accomplished by the multistage decimator with the complex coefficient bandpass digital filters (BPFs), which construct the bandpass Hilbert transformers. Most of the complex coefficient BPFs in the multistage decimator can be replaced with the lowpass filters (LPFs) under some conditions, which reduces computational burden. We evaluate the signal to quantization noise ratio of the I and Q components for the sinusoidal input by computer simulation. Simulation results show that the equivalent amplitude resolution of the I and Q components can be increased by 3 bits in comparison with non-oversampling case.

In this paper we estimate the number of permutations realizable in fault-tolerant multistage interconnection networks designed to tolerate faults on any switching element. The Parallel Omega network and the INDRA network are representative types of fault-tolerate multistage interconnection networks designed to tolerate a single fault. In order to evaluate the enhancement in the function of network by preparing the hardware redundancy for fault-tolerance, we estimate the number of permutations realizable in fault-tolerant networks. This result enables us to set up a standard to evaluate the hardware redundancy required to tolerate multifaults from the viewpoint of the enhancement of network function. This paper concludes that in the case where the number of inputs is up to 32 the increase ratio of the number of realizable permutations is no more than 1/0.73 even if the tolerance to multifaults is prepared instead of the tolerance to a single fault.

This paper describes the architecture and new circuit technologies of a proposed Pixel (bit) -Aligned Triple-port DRAM (PATDRAM). The PATDRAM has a 270 K word 16 b Random Access Memory (RAM), a 512 word 8 b Serial Access Memory-(a) (SAMa) and a 1024 word 4 b Serial Access Memory-(b) (SAMb). The random port, serial-a and serial-b port can be operated by three independent synchronous clocks. In these three ports, word data can be aligned to the location of an arbitrary bit position. Data transfer from SAMb to RAM can be individually masked by transfer mask data. The RAM operates by 33 MHz synchronous clock and two SAMs operate by 40 MHz clocks. Novel architecture of the PATDRAM accelerates graphics performance and simplifies in multimedia systems which manage both realtime video and computer graphics data, and also accelerates graphics performance in both two-dimensional (2D) and three-dimensional (3D) graphics systems. PATDRAM was designed using a 0.6 µ double metal, triple poly, stacked capacitor, CMOS process technology in a 10.98 mm9.88 mm die area integrated 4.4 Mb RAM, 8 Kb SAM, 4 Kb transfer mask register and 5 Kgate logic.

The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm2 cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm2 cell size for a 0.5 µm 64 Mbit flash memory, is described.

A distributive serial multi-bit parallel test scheme for large capacity DRAMs has been developed. The scheme, distributively and serially, extracts and compares the data from cells on a main word-line. This test scheme features a high parallel test bit number, little restriction on test patterns, and, with regard to cells and sense-amplifiers, the same operational margin as normal mode. In an experimental 256-Mb DRAM, the scheme successfully has achieved a 512-bit parallel test.

This paper presents a new line extraction method to capture vectors based on contours and skeletons from line drawing raster images in which the lines are touched by characters or other lines. Conventionally, two line extraction methods have generally been used. One is a thinning method. The other is a medial line extraction method based on parallel pairs of contours. The thinning method tends to distort the extracted lines, especially at intersections and corners. On the other hand, the medial line extraction method has a poor capability as regards capturing correct lines at intersections. Contours are able to maintain edge shapes well, while skeletons preserve topological features; thus, a combination of these features effectively leads to the best fitting line. In the proposed method, the line which best fits the original image is selected from among various candidate lines. The candidates are created from several merged short skeleton fragments located between pairs of short contour fragments. The method is also extended to circular arc fitting. Experimental results show that the proposed line fitting method is effective.

An efficient algorithm is presented for solving nonlinear resistive networks. In this algorithm, the techniques of the piecewise-linear homotopy method are introduced to the Katzenelson algorithm, which is known to be globally convergent for a broad class of piecewise-linear resistive networks. The proposed algorithm has the following advantages over the original Katzenelson algorithm. First, it can be applied directly to nonlinear (not piecewise-linear) network equations. Secondly, it can find the accurate solutions of the nonlinear network equations with quadratic convergence. Therefore, accurate solutions can be computed efficiently without the piecewise-linear modeling process. The proposed algorithm is practically more advantageous than the piecewise-linear homotopy method because it is based on the Katzenelson algorithm that is very popular in circuit simulation and has been implemented on several circuit simulators.

A design rule relaxation approach is one of the most important requirements for high density DRAMs. The approach relaxes the design rule of a element in comparison with the memory cell size and provides high density DRAMs with the minimum development of a scaled-down MOS structure and a fine patterning lithography process. This paper describes two design rule relaxation approaches, a close-packed folded (CPF) bit-line cell array layout and a Boosted Dual Word-Line scheme. The CPF cell array provides 1.26 times wider active area pitch and maximum 1.5 times wider isolation width. The Boosted Dual Word-Line scheme provides 2n times wider 1st Al pitch on memory cell array, double word-line driver pitch and 1.5 times larger design rule for 1st Al and contacts under 1st Al. Especially wide design rule of the Boosted Dual Word-Line scheme provides several times depth of focus (DOF) for 1st Al wiring which gives several times higher storage node and larger capacitance for capacitor over bit-line (COB) stacked capacitor cells. These approaches are successfully implemented in a 4 Mb DRAM test chip with a 0.91.8 µm2 memory cell.

Thin (Ba0.75Sr0.25)TiO3 (BST) films to be used as dielectric materials in 256 Mbit DRAM capacitors were investigated. These films were deposited by an rf-sputtering method at substrate temperatures of 480 to 750. As substrate temperature increases, the dielectric constant to the films also increases, from 230 to 550. BST films prepared at temperatures higher than 700 show larger current leaks than films prepared at lower temperatures. A dielectric constant of 250, corresponding to a silicon oxide equivalent thickness (teq) of 0.47 nm, and a leak current density about 110-8 A/cm2 were obtained in 30-nm-thick film deposited at 660. Both of these values are sufficient for use in a 256 Mbit DRAM capacitor.

A new method for the DRAM soft-error evaluation was developed. By using a focused proton microprobe as a radiation source, and scanning it on a memory cell plane, local sensitive structure of memory cells against soft-errors could be investigated with a form of the susceptibility mapping. Cell mode and bit-line mode soft-errors could be clearly distinguished by controlling the incident location and the proton dose, and it was also found that the incident beam within 4 µm around the monitored memory cell caused the soft-error. The retrograde well formed by the MeV ion implantation technology was examined by this method. It was confirmed that the B+ layers in the retrograde well were a sufficient barrier against the charge collection. The generation rate of the electron-hole pairs and the charge collection into n+ layers with a retrograde well and a conventional well were estimated by the device simulator, and were explained the experimental results.

This paper newly estimates the yield suppression for 1.5 V-1 Gbit DRAM caused by threshold voltage variation of MOSFET due to microscopic fluctuations in dopant distributions within the channel region and points out the limitation of the conventional redundancy techniques. The yield suppression is estimated for four main circuit blocks, the memory cell transfer transistor, bit line sense amplifier S/A, I/O line differential amplifier D/A, and the peripheral circuit. It is newly found that for 1.5 V-1 Gbit DRAM due to the effect of the newly estimated threshold voltage variation of MOSFET the bit failures of memory cells become the most dominant failure mode and the failure of D/A which can be ignored for 64 Mbit DRAM level can no longer be neglected. Furthermore, the novel optimized redundancy technique for replacing these failure is described.

This paper describes modeling and simulation of submicron NMOSFET current drive focusing on carrier velocity-saturation effects. A new simple analytical model is proposed which predicts a significant degradation of drain current in sub- and quarter-micron NMOSFET's. Numerical two-dimensional simulations clarify that the degradation is namely caused by high lateral electric field along the channel, which leads to deep velocity-saturation of channel electrons even at the source end. Experimental data of NMOSFET's, with gate oxide thickness (Tox) of 9-20 nm and effective channel lengths (Leff) of 0.35-3.0 µm, show good agreement with the proposed model. It is found that the maximum drain current at the supply voltage of Vdd=3.3 V is predicted to be proportional to Leff0.54 in submicron NMOSFET's, and this is verified with experiments.

A software package has been developed for simulating complex silicon and heterostructure devices in 3D. Device geometries are input with a mouse-driven geometric modeler, thus simplifying the definition of complex 3D shapes. Single components of the device are assembled through boolean operations. Tetrahedra are used for grid generation, since any plane-faced geometry can be tessellated with tetrahedra, and point densities can be adapted locally. The use of a novel octree-like data structure leads to oriented grids where desirable. Bad angles that prevent the convergence of the control volume integration scheme are eliminated mostly through topological transformations, thus avoiding the insertion of many redundant grid points. The discretized drift-diffusion equations are solved with an iterative method, using either a decoupled (or Gummel) scheme, or a fully coupled Newton scheme. Alternatively, generated grids can be submitted to a Laplace solver in order to calculate wire capacitances and resistances. Several examples of results illustrate the flexibility and effectiveness of this approach.

Leakage enhancement after an ESD event has been analyzed for output buffer LDD MOSFETs. The HBM ESD failure threshold for the LDD MOSFETs is only 200-300 V and the failure is the leakage enhancement of the off-state MOSFETs called as "soft breakdown" leakage. This leakage enhancement is supposed to be caused by trapped electrons in the gate oxide and/or creation of interface states at the gate overlapped drain region due to snap-back stress during the ESD event. The mechanism of the lekage can be explained by band-to-band and/or interface state-to-band tunneling of electrons. The improvement of the HBM ESD threshold has been also evaluated by using two types of drain engineering which are additional arsenic implantation for the output LDD MOSFETs and "offset" gate MOSFET as a protection circuit for the output pins. By using these drain engineering, the threshold can be improved to more than 2000 V.

Computing devices have reached data frequencies of 100 MHz, and have created a need for small-amplitude impedance-matched buses. We simulated signal transmission characteristics of two basic driver circuits, push-pull and open-drain,for a synchronous DRAM I/O bus. The push-pull driver caused less signal distortion with parasitic inductance and capacitance of packages, and thus has higher frequency limits than the open-drain GTL type. We describe a bus system using push-pull drivers which operates at over 125 MHz. The bus line is 70 cm with 8 I/O loads distributed along the line, each having 25 nH7pF parasitic inductance and capacitance.

We studied minority carrier collection in high-density stacked-capacitor DRAM cells using a three-dimensional device simulator. We estimated the collected charge for incident angle, location, and junction size and showed that, compared to the conventional structure by a twin-well process, an n-well-guarded cell array fabricated using a triple-well process effectively reduced the charge injected into cells. The reduction was because the n-well absorbed most of the electrons. A so-called "size-effect" did exist and smaller junctions performed better. We concluded that storage capacitance in a 256 M-bit DRAM cell could be reduced, compared to that in previous devices, which would, in turn, help reduce costs in fabricating high-density DRAM.

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.