A network of sensors can be used to obtain state based data from the area in which they are deployed. To reduce costs, the data sent via intermediate sensors to a sink are often aggregated. In this letter, we introduce Self-Construction of Aggregation Tree (SCAT) scheme which uses a novel data aggregation scheme utilizing the knowledge of the mobile node and the infrastructure (static node tree) in gathering the data from the mobile node. The static nodes can construct a near- optimal aggregation tree by themselves, using the knowledge of the mobile node, which is a process similar to forming the centralized aggregation tree.

To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design.

In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.

A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.

Topological structure of peer-to-peer (P2P) networks affects their operating performance. Thus, various models have been proposed to construct an efficient topology for the P2P networks. However, due to the simultaneous failures of peers and other disastrous events, it is difficult to maintain the originally designed topological structure that provides the network with some performance benefits. For this reason, in this paper we propose a simple local rewiring method that changes the network topology to have small diameter as well as highly clustered structure. Moreover, the presented evaluation study shows how these topological properties are involved with the performance of P2P networks.

This paper investigates whether the self-heating effect in short intra-block wires will become apparent with technology scaling. These wires seem to have good thermal radiation characteristics, but we validate that the self-heating effect in local signal wires will be greater than that in optimal repeater-inserted global wires. Our numerical experiment shows that the maximum temperature increase from the silicon junction temperature will reach 40.4 in a steady state at a 14-nm process. Our attribution analysis also demonstrates that miniaturizing the area of wire cross-section exacerbates self-heating as well as using low-κ material and increased power dissipation in advanced technologies below 28 nm. It is revealed that the impact of self-heating on performance in local wires is limited, while underestimating the temperature may cause an unexpected reliability failure.

Custody transfer in delay tolerant networks (DTNs) provides reliable end-to-end data delivery by delegating the responsibility of data transfer among special nodes (custodians) in a hop-by-hop manner. However, storage congestion occurs when data increases and/or the network is partitioned into multiple sub-networks for a long time. The storage congestion can be alleviated by message ferries which move around the network and proactively collect data from the custodians. In such a scenario, data should be aggregated to some custodians so that message ferries can collect them effectively. In this paper, we propose a scheme to aggregate data into selected custodians, called aggregators, in a fully distributed and autonomous manner with the help of evolutionary game theoretic approach. Through theoretical analysis and several simulation experiments, taking account of the uncooperative behavior of nodes, we show that aggregators can be selected in a self-organized manner and the number of aggregators can be controlled to a desired value.

This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32 nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32 nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.

In this paper, we describe several approaches to address the challenges of the network of the future. Our main hypothesis is that the Future Internet must be designed for the environment of applications and transport media of the 21st century, vastly different from the initial Internet's life space. One major requirement is the inherent support for mobile and wireless usage. A Future Internet should allow for the fast creation of diverse network designs and paradigms and must also support their co-existence at run-time. We detail the technical and business scenarios that lead the development in the EU FP7 4WARD project towards a framework for the Future Internet.

A new generation network is requested to accommodate an enormous number of heterogeneous nodes and a wide variety of traffic and applications. To achieve higher scalability, adaptability, and robustness than ever before, in this paper we present new network architecture composed of self-organizing entities. The architecture consists of the physical network layer, service overlay network layer, and common network layer mediating them. All network entities, i.e. nodes and networks, behave in a self-organizing manner, where the global behavior emerges through their operation on local information and direct and/or indirect mutual interaction. The center of the architecture is so-called self-organization engines, which implement nonlinear self-organizing dynamics originating in biology, physics, and mathematics. In this paper, we also show some examples of self-organization engines.

This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07 bits without calibration and 6.74 bits with calibration up to 500 MHz input signal at sampling rate of 600 MSps. It dissipates 98.5 mW on 1.2-V supply. FoM is 1.54 pJ/conv.

In photonic label routing networks, recognition of optical labels is one of the key functions. We have proposed passive waveguide-type devices for recognition of optical labels coded in quadri-phase-shift-keying (QPSK) form. In this paper, we consider wavelength dependence of the devices. The basic module of the proposed device consists of a 3-dB directional coupler, two Y-junctions, and an asymmetric X-junction. The Y-junction and an asymmetric X-junction have basically no wavelength dependence. Although the 3-dB directional coupler has weak wavelength dependence, the device for two-symbol label recognition is found to work in wavelength 1.5-1.6 µm. The performance of the device is confirmed by simulation using beam propagation method (BPM).

This paper presents a novel approach for robot localization using landmark maps. With recent progress in SLAM researches, it has become crucial for a robot to obtain and use large-size maps that are incrementally built by other mapper robots. Our localization approach successfully works with such incremental and large-size maps. In literature, RANSAC map-matching has been a promising approach for large-size maps. We extend the RANSAC map-matching so as to deal with incremental maps. We combine the incremental RANSAC with an incremental LSH database and develop a hybrid of the position-based and the appearance-based approaches. A series of experiments using radish dataset show promising results.

We present a 60-GHz wireless through-repeater system based on self-heterodyne transmission scheme with the potential to optimize the carrier-to-interference and noise ratio (CINR) performance according to the transmission distance. The phase-noise degradation through a 60-GHz repeater link is not a serious concern when we employ the self-heterodyne transmission scheme. Multichannel interferences caused by third-order intermodulation distortions are efficiently suppressed by setting a high power ratio of LO carrier to RF signals in the self-heterodyne transmission. However, this high power ratio results in a lower carrier-to-noise ratio (CNR) and becomes unsuitable for improving link performance if the transmission distance increases. In order to facilitate a solution, we propose and make an embodiment of 60 GHz self-heterodyne transmitters that provide flexible control over the power ratio of LO to RF in a range of 10 dB ranges. With them, we successfully demonstrate terrestrial digital broadcasting signals on five channels and optimize their performance for wireless through-repeater applications.

Our paper proposes a low power delay element with many other valuable characteristics for asynchronous circuits in the bundled-data implementation. Delay elements are frequently utilized to interact with asynchronous environment for revealing the current status of the bundled-data asynchronous circuits. Thus, a notable portion of the total energy is consumed by the delay elements for this kind of designs. Moreover, constructing a specific delay on a chip is a difficult task for recent CMOS technology. An extreme low power asymmetrical delay element with post-chip adjustment feature was developed mainly for solving these issues. Our initial intention was to develop a programmable delay element for asynchronous data path components. The proposed delay element is also suitable for many other applications requiring low power constraint. In addition to the programmability, the delay element also demonstrated efficiently characteristics such as good tolerance to process and temperature variations on the delay. Our delay element is equivalent to approximately the average power of a 4-stage inverter chain. A large delay can be obtained by cascaded scheme with nearly zero handshaking overhead. All arguments were cautiously verified by the post-layout simulation setup using TSMC 0.35 µm and 0.18 µm technologies under all extreme corners.

The self-organized microwrinkles can serve as a surface alignment layer to align nematic liquid crystals, which is primarily based on the groove mechanism. The azimuthal anchoring energy is discussed and estimated from the groove topography and the actual twist angle in the twisted nematic cell.

Kiyomoto-Fukushima-Tanaka proposed a perfectly anonymous attribute authentication scheme that realizes unidentifiable and untraceable authentication with offline revocation checking. The Kiyomoto-Fukushima-Tanaka scheme uses a self-blindable certificate that a user can change randomly. Thus, the certificate is modified for each authentication and the authentication scheme has the unidentifiable property and the untraceable property. However, in this letter, we show that the Kiyomoto-Fukushima-Tanaka scheme is insecure against the impersonation attack.

Self-Organizing Map (SOM) is a powerful tool for the exploratory of clustering methods. Clustering is the most important task in unsupervised learning and clustering validity is a major issue in cluster analysis. In this paper, a new clustering validity index is proposed to generate the clustering result of a two-level SOM. This is performed by using the separation rate of inter-cluster, the relative density of inter-cluster, and the cohesion rate of intra-cluster. The clustering validity index is proposed to find the optimal numbers of clusters and determine which two neighboring clusters can be merged in a hierarchical clustering of a two-level SOM. Experiments show that, the proposed algorithm is able to cluster data more accurately than the classical clustering algorithms which is based on a two-level SOM and is better able to find an optimal number of clusters by maximizing the clustering validity index.

In this letter we give a lower bound on the worst-case time complexity of Dijkstra's three-state mutual exclusion algorithm by specifying a concrete behavior of the algorithm. We also show that our result is more accurate than the known best bound.

This paper presents an efficient algorithm for large-scale multi-system learning task. The proposed architecture, referred to as the 'RBF×SOM', is based on the SOM2, that is, a'SOM of SOMs'. As is the case in the modular network SOM (mnSOM) with multilayer perceptron modules (MLP-mnSOM), the aim of the RBF×SOM is to organize a continuous map of nonlinear functions representing multi-class input-output relations of the given datasets. By adopting the algorithm for the SOM2, the RBF×SOM generates a map much faster than the original mnSOM, and without the local minima problem. In addition, the RBF×SOM can be applied to more difficult cases, that were not easily dealt with by the MLP-mnSOM. Thus, the RBF×SOM can deal with cases in which the probability density of the inputs is dependent on the classes. This tends to happen more often as the input dimension increases. The RBF×SOM therefore, overcomes many of the problems inherent in the MLP-mnSOM, and this is crucial for application to large scale tasks. Simulation results with artificial datasets and a meteorological dataset confirm the performance of the RBF×SOM.