Miniaturized broadband antennas combining a fractal pattern and a self-complementary structure are demonstrated for UWB applications. Using four kinds of fractal patterns generated with an octagon initiator, similar to a self-complementary structure, we investigate the effect of the fractal pattern on broadband performance. The lower band-edge frequency of the broad bandwidth is decreased by the reduced constant input impedance, which is controlled by the vacant area size inside the fractal pattern. The reduced constant input impedance is shown to be produced by the extended current distribution flowing along the vacant areas. Given the results, miniaturized broadband antennas, impedance-matched to 50 Ω, are designed and fabricated. The measured return loss was better than 10 dB between 2.95 and 10.7 GHz with a size of 2712.5 mm. The lower band-edge frequency was reduced by 28% compared with the initiator.

For large-scale sensor networks, multiple sinks are often deployed in order to reduce source-to-sink distance and thus cost of data delivery. However, having multiple sinks may work against cost reduction, because routes from sources can diverge towards different sinks which reduces the benefit of in-network data aggregation. In this letter we propose a self-clustering data aggregation protocol (SCAP) that can benefit from having multiple sinks as well as joint routes. In SCAP, nodes which detect the event communicate with each other to aggregate data between themselves, before sending the data to the sinks. The self-clustering extends network lifetime by reducing energy consumption of nodes near the sinks, because the number of paths in which the packets are delivered is reduced. A performance comparison with existing protocols L-PEDAP and LEO shows that SCAP can conserve energy and extend network lifetime significantly, in a multi-sink environment.

Developing a rapid prototyping environment utilizing hardware description languages (HDLs) and conventional FPGAs can help ease and conquer the difficulties caused by the complexity of asynchronous digital systems and the advance of VLSI technology recently. We proposed a design flow and a FPGA template for implementing generalized C-element (gC) style asynchronous controllers. Utilizing conventional FPGA synthesis tools, self-timed bundled-data function modules can be realized with some effort on timing validation. The proposed design flow with FPGA-based realization approach is a very effective design methodology for rapid prototyping and functionality validation. This work could be useful for the early stage of performance estimation, power reduction exploration, circuits design training, and many other applications regarded asynchronous circuits. In this paper, the proposed FPGA-based asynchronous circuit design flow, a hands-on design tutorial, a generalized C-element template, and a list of synthesized benchmark circuits are documented and discussed in detail.

A 65 nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370 mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6 V, 27 fJ/operation at 264 MHz.

In this paper, for networked systems, synthesis of self-triggered controllers is addressed. In the proposed method, the control input and the sampling time such that a given cost function is minimized are computed simultaneously. First, the optimal control problem of continuous-time linear systems is rewritten as that of systems with integral continuous-time dynamics. Next, this problem is approximately reduced to a linear programming problem. The proposed method can be applied to model predictive control. Finally, the effectiveness of the proposed method is shown by a numerical example.

The susceptibility of a static random access memory (SRAM) core against static and dynamic variation of power supply voltage is evaluated, by using on-chip diagnosis structures of memory built-in self testing (MBIST) and on-chip voltage waveform monitoring (OCM). The SRAM core of interest in this paper is a synthesizable version applicable to general systems-on-a-chip (SoC) design, and fabricated in a 90 nm CMOS technology. RF power injection to power supply networks is quantified by OCM. The number of resultant erroneous bits as well as their distribution in the cell array is given by MBIST. The frequency-dependent sensitivity reflects the highly capacitive nature of densely integrated SRAM cells.

In this paper, the author proposes an electromagnetic coupling fed inverted-FL antenna design. The inverted-FL antenna with a self-complementary structure has been reported as a way to achieve a constant impedance of 188 ohms without the need for a matching load, since the axially symmetric self-complementary antenna has constant impedance, even though it has a finite structure. This design has been realized by integrating an inverted-F antenna with a self-complementary structure for achieving a broadband characteristic and an inverted-L element for operation on a frequency lower than the minimum frequency of the antenna. The proposed antenna realizes a broadband characteristic without attaching the matching load and the impedance transformer to match 50 ohms. The impedance transformer necessary for the inverted-FL antenna with a self-complementary structure is removed by using an electromagnetic coupling feed structure. This antenna, which has a volume of 101045 mm3, obtained broadband and multi-band characteristics covering the GSM850/GSM900/DCS/PCS/UMTS2100/UMTS2600 bands and the 2.5 G/3.5 G bands for Mobile-WiMAX in simulation and measurement.

In the present paper, we address the problem of extrapolating group proximities from member relations, which we refer to as the group proximity problem. We assume that a relational dataset consists of several groups and that pairwise relations of all members can be measured. Under these assumptions, the goal is to estimate group proximities from pairwise relations. In order to solve the group proximity problem, we present a method based on embedding and distribution mapping, in which all relational data, which consist of pairwise dissimilarities or dissimilarities between members, are transformed into vectorial data by embedding methods. After this process, the distributions of the groups are obtained. Group proximities are estimated as distances between distributions by distribution mapping methods, which generate a map of distributions. As an example, we apply the proposed method to document and bacterial flora datasets. Finally, we confirm the feasibility of using the proposed method to solve the group proximity problem.

The primary challenges faced by wireless sensor networks are how to construct the shortest spanning tree and how to determine the optimal sink node position in terms of minimizing the data transmission times and their variances for data gathering from all sensor nodes to a sink node. To solve these two problems, we propose a novel algorithm that uses the polygonal affine shortening algorithm with flow aggregation. This algorithm enables a wireless sensor network that has movable sensor nodes and one movable sink node to self-organize the shortest spanning tree and self-determine the optimal sink node position in a fully distributed manner. We also show that our algorithm is faster than the existing shortest path algorithm in terms of computational complexity.

Thin film glucose biosensors were fabricated with organic/inorganic hybrid films based on glucose oxidase (GOx) and Prussian Blue nano-clusters. The biosensors composed of hybrid films were characterized by the low operating potential and the advantage to interference-free detection. In this research, we employed two kinds of thin films for GOx immobilization: Langmuir-Blodgett (LB) and self-assembled monolayer (SAM). The LB film immobilizes GOx in its inside through the electrostatic force, while the SAM immobilizes GOx with the covalent bond. The sensors with LB film produced a relatively high current signal, while the non-linear behavior and a low stability were recognized. On the other hand, the sensors with SAM presented a good linear relationship and a very stable performance.

This paper studies the 2-adic complexity of the self-shrinking sequence under the relationship between 2-adic integers and binary sequences. Based on the linear complexity and the number of the sequences which have the same connection integer, we conclude that the 2-adic complexity of the self-shrinking sequence constructed by a binary m-sequence of order n has a lower bound 2n-2-1. Furthermore, it is shown that its 2-adic complexity has a bigger lower bound under some circumstances.

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigated by impedance spectroscopy (IS). The IS of polymer OFETs with self-aligned electrodes reveals frequency-dependent channel formation process and the frequency response in FET structure.

We propose frequency-domain optical code-division-multiplexing (CDM) employing quadrature-amplitude-modulation (QAM) using two of multi-level (M-ary) data generated based on electrical-domain spatial code spreading. Its spectral efficiency is enhanced compared to the conventional scheme with amplitude-shift-keying (ASK) using only one of M-ary data. Although it demands the recovery of amplitude and optical phase information, the practicality of the receiver is retained with self-homodyne detection using a phase-shift-keying (PSK) pilot light. Performance is theoretically evaluated and the optimal parameters are derived. Finally, the feasibility of the proposed technique is experimentally confirmed.

This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.

This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.

This paper proposes a built-in self-test (BIST) scheme for noise-tolerant testing of a digital-to-analogue converter (DAC). The proposed BIST calculates the differences in output voltages between a DAC and test modules. These differences are used as the inputs of an integrator that determines integral nonlinearity (INL). The proposed method has an advantage of random noise cancelation and achieves a higher test accuracy than do the conventional BIST methods. The simulation results show high standard noise-immunity and fault coverage for the proposed method.

This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.

In this paper, a 65 nm 1.2 V 7-bit 1GSPS folding-interpolation A/D converter with a digitally self-calibrated vector generator is proposed. The folding rate is 2 and the interpolation rate is 8. A self-calibrated vector generation circuit with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage caused by process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65 nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87 mm2 and the power consumption is about 110 mW with a 1.2 V power supply. The measured SNDR is about 39.1 dB when the input frequency is 250 MHz at a 1 GHz sampling frequency. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRPTM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined.

As the demand for spectrum for future wireless communication services increases, cognitive radio technology has been developed for dynamic and opportunistic spectrum access, which enables the secondary users to use the underutilized licensed spectrum of the primary users. In particular, the recent studies on the MAC protocol for dynamic and opportunistic access have focused on sensing and using the vacant spectrum efficiently. Under the ad-hoc network environment, how the secondary users use the unused channels by the primary users affects the efficient utilization of channels and a cognitive radio system is required to follow the rapid and frequent changes in channel status. In this paper, we propose a self-scheduling multi-channel cognitive MAC (SMC-MAC) protocol, which allows multiple secondary users to transmit data though the sensed idle channels by two cooperative channel sensing algorithms, i.e., fixed channel sensing (FCS) and adaptive channel sensing (ACS), and by slotted contention mechanism to exchange channel request information for self-scheduling. The performance of the proposed SMC-MAC protocol is investigated via analysis and simulations. According to the results, the proposed SMC-MAC protocol is effective in allowing multiple secondary users to transmit data frames effectively on multi-channels and adaptively in response to the primary users' traffic dynamics.