In this letter, we present a fast image/video super resolution framework using edge and nonlocal constraint. The proposed method has three steps. First, we improve the initial estimation using content-adaptive bilateral filtering to strengthen edge. Second, the high resolution image is estimated by using classical back projection method. Third, we use joint content-adaptive nonlocal means filtering to get the final result, and self-similarity structures are obtained by the low resolution image. Furthermore, content-adaptive filtering and fast self-similarity search strategy can effectively reduce computation complexity. The experimental results show the proposed method has good performance with low complexity and can be used for real-time environment.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm2.

In this paper, several spiral inductors with various ground clearance structures and turns were investigated to achieve noise suppression up to the fourth harmonic (3.2 GHz) regime of DDR3-1600. Their performances were characterized in terms of their capability to effectively suppress simultaneous switching noise (SSN) in the frequency region of interest. For a wider noise suppression bandwidth, a spiral inductor with large ground clearance, which provides a high self resonance frequency (SRF) as well as high inductances, was implemented. The proposed spiral inductor exhibited good noise suppression characteristics in the frequency domain and achieved 50% voltage fluctuation reduction in the time domain, compared to the identical 4-turn spiral without pattern ground structure.

Self-triggered control is a control method that the control input and the sampling period are computed simultaneously in sampled-data control systems, and is studied in the field of networked control systems. In this paper, a new approach for self-triggered control is proposed based on the model predictive control (MPC) method. First, self-triggered MPC with delay compensation in which the delay-compensation input is introduced is newly formulated. Next, in order to efficiently solve this MPC problem, the optimal control problem with horizon one is formulated, and an approximate solution method is derived. Finally, the effectiveness of the proposed approach is shown by a numerical example.

Temporal Self-Similarity Matrix (SSM) based action recognition is one of the important approaches of single-person oriented action analysis in computer vision. In this study, we propose a new kind of SSM and a fast computation method. The computation method does not require time-consuming pre-processing to find bounding boxes of the human body, instead it processes difference images to obtain action patterns which can be done very quickly. The proposed SSM is experimentally confirmed to have high power/capacity to achieve a better classification performance than four typical kinds of SSMs.

In this paper we show that self synchronous circuits can provide robust operation in both soft error prone and low voltage operating environments. Self synchronous circuits are shown to be self checking, where a soft error will either cause a detectable error or halt operation of the circuit. A watchdog circuit is proposed to autonomously detect dual-rail '11' errors and prevent propagation, with measurements in 65 nm CMOS showing seamless operation from 1.6 V to 0.37 V. Compared to a system without the watchdog circuit size and energy-per-operation is increased 6.9% and 16% respectively, while error tolerance to noise is improved 83% and 40% at 1.2 V and 0.4 V respectively. A circuit that uses the dual-pipeline circuit style as redundancy against permanent faults is also presented and 40 nm CMOS measurement results shows correct operation with throughput of 1.2 GHz and 810 MHz at 1.1 V before and after disabling a faulty pipeline stage respectively.

When we apply a voltage to a supported lipid bilayer self-spreading through a nanometer-scale gap (nanogap), the effects can be divided into two types. One is that there is no voltage-dependent change in the self-spreading behavior. Namely, the lipid bilayer passes through a nanogap without any stagnation. The other reveals that the self-spreading of a lipid bilayer can be controlled by an electric field modulation between nanogap electrodes. As a mechanism for these phenomena, we have proposed an electrostatic trapping model, in which the relationship between the thickness of an electric double layer and the nanogap spacing plays a crucial role. Here, to confirm the validity of this mechanism, we investigated the ionic concentration dependence of an electrolyte solution on the self-spreading behavior, which enabled us to tune the thickness of the electric double layer precisely. The result exhibited a certain threshold for controlling the self-spreading behavior. We also approximated the electric potential in the nanogap by using the Debye-Huckel equation. Our calculation result was in good agreement with the ionic concentration dependence experiments, suggesting the validity of our proposed mechanism. The results described in this work provide useful information regarding the realization of nanobio devices and the fundamental study of nanoelectronics.

In this paper, we investigate a relationship between the length-decreasing self-reducibility and the many-one-like reducibilities for partial multivalued functions. We show that if any parsimonious (many-one or metric many-one) complete function for NPMV (or NPMVg) is length-decreasing self-reducible, then any function in NPMV (or NPMVg) has a polynomial-time computable refinement. This result implies that there exists an NPMV (or NPMVg)-complete function which is not length-decreasing self-reducible unless P = NP.

We report a trial of 100-GS/s optical quantization with 5-bit resolution using soliton self-frequency shift (SSFS) and spectral compression. We confirm that 100-GS/s 5-bit optical quantization is realized to quantize a 5.0-GHz sinusoid electrical signal in simulation. In order to experimentally verify the possibility of 100-GS/s 5-bit optical quantization, we execute 5-bit optical quantization by using two sampled signals with 10-ps intervals.

In the construction of a no-linear key-stream generator, self-shrinking is an established way of getting the binary pseudo-random periodic sequences in cryptography design. In this paper, using the theoretical analysis, we mainly study the self-shrinking sequence based on the l-sequence, and the theoretical results reflect its good cryptography properties accurately, such that it has the last period T = pe(p-1)/2 when T is an odd number, and the expected value of its autocorrelation belongs to {0,1/T and the variance is O(T/ln4T). Furthermore, we find that the 2-adic complexity of the self-shrinking sequence based on the l-sequence is large enough to resist the Rational Approximation attack.

In our privious paper, we proposed an algorithm that determines delay times of a timed Petri net from the structural information of a signaling pathway, but Petri net structures containing cycles and inhibitory arcs were not considered. This paper provides conditions for cycle-contained Petri nets to have reasonable delay times. Furthermore, handling of inhibitory arcs are discussed in terms of the reaction rate of inhibitory interaction in signaling pathway, especially the conversion process of Petri net with inhibitory arc to the one without inhibitory arc is given.

Streak cameras are now widely used for measurements of ultra short phenomena, such as those in semi conductor luminescence and plasma gaseous discharge. To further improve the temporal resolution and carry out higher-dimensional measurements, it is necessary to understand the electron beam behavior in detail. Thus, numerical simulations play an important role in the analysis of the streak camera. The authors have been working on the development of a numerical simulation code that uses the finite difference method (FDM) for electric field analysis, the Runge-Kutta (R-K) method for charged particle motion determination, and the particle-in-cell (PIC) method for charge density calculation. However, the use of the PIC method leads to inaccuracy in the charge density calculation in cases of high-density electron beams. To improve the accuracy of the conventional analysis of the streak camera, we perform the boundary element (BE) analysis of the streak camera.

Self-encoded spread spectrum (SESS) derives its spreading codes from the random information source rather than using traditional pseudo-random codes. It has been shown that the memory in SESS modulated signals not only can deliver a 3 dB gain in additive white Gaussian noise (AWGN) channels, but also can be exploited to achieve time diversity and robust bit-error rate (BER) performance in fading channels. In this paper, we propose an extension to SESS, namely coded-sequence self-encoded spread spectrum (CS-SESS), and show that it can further improve the BER performance. We describe the CS-SESS scheme and present the theoretical analysis and simulation results for AWGN and fading channels. Iterative detector is developed to exploit the inherent temporal diversity of CS-SESS modulation. The simulation results show that it can achieve the expected 4.7 dB gain with a complexity that increases linearly with the spreading sequence length under AWGN. In Rayleigh fading channel, it can effectively mitigate the fading effects by exploiting the overall diversity gain. Chip interleaving is shown to yield a performance improvement of around 4.7 dB when compared to an chip interleaved direct sequence spread spectrum (DSSS) system.

Real-time on-chip measurement of bit error rate (BER) for high-speed analog-to-digital converters (ADCs) does not only require expensive multi-port high-speed data acquisition equipment but also enormous post-processing. This paper proposes a low-cost built-in-self-test (BIST) circuit for high-speed ADC BER test. Conventionally, the calculation of BER requires a high-speed adder. The presented method takes the advantages of Gray coding and only needs simple logic circuits for BER evaluation. The prototype of the BIST circuit is fabricated along with a 5-bit high-speed flash ADC in a 90-nm CMOS process. The active area is only 90 µm 70 µm and the average power consumption is around 0.3 mW at 700 MS/s. The measurement of the BIST circuit shows consistent results with the measurement by external data acquisition equipment.

Microwave imaging techniques, in particular synthetic aperture radar (SAR), are able to obtain useful images even in adverse weather or darkness, which makes them suitable for target position or feature estimation. However, typical SAR imagery is not informative for the operator, because it is synthesized using complex radio signals with greater than 1.0 m wavelength. To deal with the target identification issue for imaging radar, various automatic target recognition (ATR) techniques have been developed. One of the most promising ATR approaches is based on neural network classification. However, in the case of SAR images heavily contaminated by random or speckle noises, the classification accuracy is severely degraded because it only compares the outputs of neurons in the final layer. To overcome this problem, this paper proposes a self organized map (SOM) based ATR method, where the binary SAR image is classified using the unified distance matrix (U-matrix) metric given by the SOM. Our numerical analyses and experiments on 5 types of civilian airplanes, demonstrate that the proposed method remarkably enhances the classification accuracy, particular in lower S/N situations, and holds a significant robustness to the angular variations of the observation.

This paper presents a self-clustering algorithm to detect symmetry in images. We combine correlations of orientations, scales and descriptors as a triple feature vector to evaluate each feature pair while low confidence pairs are regarded as outliers and removed. Additionally, all confident pairs are preserved to extract potential symmetries since one feature point may be shared by different pairs. Further, each feature pair forms one cluster and is merged and split iteratively based on the continuity in the Cartesian and concentration in the polar coordinates. Pseudo symmetric axes and outlier midpoints are eliminated during the process. Experiments demonstrate the robustness and accuracy of our algorithm visually and quantitatively.

In a shared medium communication system, mobile users contend for channel access according to a given set of rules to avoid collisions and achieve efficient use of the medium. If one or more users do not comply with the agree rules either due to selfish or malicious behaviours, they will cause some impacts on the system performance, especially to the well-behaved users. In this paper, we consider the problem of user misbehaviours on the performance of a wireless infrastructure-based network using reservation-based MAC protocols. Key misbehaving strategies possible in such a network are identified and explained. To quantify the impact of these misbehaviours upon the network performance, three different misbehaving scenarios are developed to allow a systematic investigation of each misbehaving strategy. For each scenario, we have derived mathematical formulations for evaluating and analyzing the key performance metrics, i.e., probabilities of success of well-behaved and misbehaved users and the fairness index. Numerical results show that the presence of misbehaviours can cause different levels of damage depending on the misbehavior strategy used. The combined multi-token and increasing permission probability strategies where the misbehaved user selfishly accesses the channel more times and with higher probabilities than allowed is shown to cause the most severe impairment of performance and fairness.

We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.

In DC/DC converters with low output voltage and high output current, the technique of synchronous rectification is widely used for improving the output efficiency. However, SR buck converters can experience the abnormal phenomenon called “self turn-on” which will occur in the low-side switch under some circuit conditions. “Self turn-on” is a malfunction of the low-side switch, basically caused by the resonance of the parasitic inductance and the parasitic capacitance. It results in noticeable power dissipation. In this paper, the phenomenon will be clearly described and investigated. With the theoretical analysis and the experimental verification, strategies that can suppress this phenomenon are proposed.

We propose a novel modular network called the Self-Evolving Modular Network (SEEM). The SEEM has a modular network architecture with a graph structure and these following advantages: (1) new modules are added incrementally to allow the network to adapt in a self-organizing manner, and (2) graph's paths are formed based on the relationships between the models represented by modules. The SEEM is expected to be applicable to evolving functions of an autonomous robot in a self-organizing manner through interaction with the robot's environment and categorizing large-scale information. This paper presents the architecture and an algorithm for the SEEM. Moreover, performance characteristic and effectiveness of the network are shown by simulations using cubic functions and a set of 3D-objects.