This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

This paper presents an improved version of multi-stage threshold decoding with a difference register (MTD-DR) for self-orthogonal convolutional codes (SOCCs). An approximate lower bound on the bit error rate (BER) with the maximum likelihood (ML) decoding is also given. MTD-DR is shown to achieve an approximate lower bound of ML decoding performance at the higher Eb/N0. The code with larger minimum Hamming distance reduces the BER in error floor, but the BER in waterfall shifts to the higher Eb/N0. This paper gives a decoding scheme that improves the BER in both directions, waterfall and error floor. In the waterfall region, a 2-step decoding (2SD) improves the coding gain of 0.40 dB for shorter codes (code length 4200) and of 0.55 dB for longer codes (code length 80000) compared to the conventional MTD-DR. The 2-step decoding that serially concatenates the parity check (PC) decoding improves the BER in the error floor region. This paper gives an effective use of PC decoding, that further makes the BER 1/8 times compared to the ordinary use of PC decoding in the error floor region. Therefore, the 2SD with effective use of parity check decoding improves the BER in the waterfall and the error floor regions simultaneously.

We consider RFID bookshelves, which detect the location of books using RFID. An RFID bookshelf has the antennas of RFID readers in the boards, and detects the location of an RFID tag attached to a book. However, the accuracy is not good with the experience of the existing system, and sometimes reads the tag of the next or even further area. In this paper, we propose a method to improve the location detection using naive Bayes classifer, and show the experimental result. We obtained 78.6% of F-measure for total 12658 instances, and show the advantage against the straightforward approach of calculating the center of gravity of the read readers. More importantly, we show the performance is less dependent of a change of layouts and a difference of books by leave-1-layout/book-out cross validation. This is favorable for the feasibility in library operation.

Due to the lack of end-to-end paths between the communication source and destination, the routing of Delay Tolerant Networks (DTN) exploits the store-carry-and-forward mechanism. This mechanism requires nodes with sufficient energy to relay and forward messages in a cooperative and selfless way. However, in the real world, the energy is constrained and most of the nodes exhibit selfish behaviors. In this paper, we investigate the performance of DTN routing schemes considering both the energy constraint and selfish behaviors of nodes. First, we model the two-hop relay and epidemic routing based on a two-dimensional continuous time Markov chain. Then, we obtain the system performance of message delivery delay and delivery cost by explicit expressions. Numerical results show that both the energy constraint and node selfishness reduce the message delivery cost at the expense of increasing the message delivery delay. Furthermore, we demonstrate that the energy constraint plays a more important role in the performance of epidemic routing than that of two-hop relay.

For the easy design of very small normal-mode helical antennas (NMHAs), an equation that helps determine the self-resonant structures of these antennas is developed. For this purpose, the expression for the capacitance of an NMHA is established. The accuracy of this design equation is confirmed by comparing the results obtained using the equation with the simulation results.

We describe the fabrication processes and electrical characteristics of two types of NbN junctions. One is a self-shunted NbN/NbNx/AlN/NbN Josephson junction, which is expected to improve the density of integrated circuits; the other is an underdamped NbN/AlNx/NbN tunnel junction with radical-nitride AlNx barriers, which has highly controllable junction characteristics. In the former, the junction characteristics were changed from underdamped to overdamped by varying the thickness of the NbNx layer. Overdamped junctions with a 6-nm-thick NbNx film exhibited a characteristic voltage of Vc = 0.8 mV and a critical current density of Jc = 22 A/cm2 at 4.2 K. In the junctions with radical-nitride AlNx barriers, Jc could be controlled in the range 0.01-3 kA/cm2 by varying the process conditions, and good uniformity of the junction characteristics was obtained.

In this paper, an artificial sub-threshold oscillating spiking neuron is presented and its response phenomena to an input spike-train are analyzed. In addition, a dynamic parameter update rule of the neuron for achieving synchronizations to the input spike-train having various spike frequencies is presented. Using an analytical two-dimensional return map, local stability of the parameter update rule is analyzed. Furthermore, a pulse-coupled network of the neurons is presented and its basic self-organizing function is analyzed. Fundamental comparisons are also presented.

A hardware description languages (HDLs) based modeling technique for asynchronous circuits is presented in this paper. A HDLs handshake package has been developed for expressing handshake-style digital systems in both VHDL and Verilog. Burst-mode and extended burst-mode (BM/XBM) circuits were used to demonstrate the usefulness of this work. This research successfully prototyped comparators, adders, RSA encoder/decoder, and several self-timed circuits for the full-custom IC and FPGAs designs. Furthermore, the HDLs handshake package implemented by this research can be utilized to develop behavioral test benches for studying and analyzing asynchronous designs. Extracting detailed timing information from asynchronous finite state machines (AFSMs), detecting delay faults for synthesized self-timed functional modules, and locating fundamental mode violation within realized AFSMs are proven applications. The anticipated HDL modeling technique and the transformation procedure are detailed in the rest of this paper.

This paper describes a nonlinear filter that can extract the image feature from noise corrupted image labeled self-quotient ε-filter (SQEF). SQEF is an improved self-quotient filter (SQF) to extract the image feature from noise corrupted image. Although SQF is a simple approach for feature extraction from the images, it is difficult to extract the feature when the image includes noise. On the other hand, SQEF can extract the image feature not only from clear images but also from noise corrupted images with uniform noise, Gaussian noise and impulse noise. We show the algorithm of SQEF and describe its feature when it is applied to uniform noise corrupted image, Gaussian noise corrupted image and impulse noise corrupted image. Experimental results are also shown to confirm the effectiveness of the proposed method.

Let q and f(x) be an odd characteristic and an irreducible polynomial of degree m over Fq, respectively. Then, suppose that F(x)=xmf(x+x-1) becomes irreducible over Fq. This paper shows that the conjugate zeros of F(x) with respect to Fq form a normal basis in Fq2m if and only if those of f(x) form a normal basis in Fqm and the compart of conjugates given as follows are linearly independent over Fq, {γ-γ-1,(γ-γ-1)q, …,(γ-γ-1)qm-1} where γ is a zero of F(x) and thus a proper element in Fq2m. In addition, from the viewpoint of q-polynomial, this paper proposes an efficient method for checking whether or not the conjugate zeros of F(x) satisfy the condition.

A novel method for single image super resolution without any training samples is presented in the paper. By sparse representation, the method attempts to recover at each pixel its best possible resolution increase based on the self similarity of the image patches across different scale and rotation transforms. The experiments indicate that the proposed method can produce robust and competitive results.

Random scattering of sensors may cause some location not to be covered. In such a case, it is useful to make use of mobile sensors that can move to eliminate the coverage holes. Wang et al [1]. proposed self-deployment schemes of mobile sensors by using Voronoi polygon. However, some coverage holes still remain after the execution of the schemes. We propose a new self-deployment scheme using the centroid (geometric center) of each sensor's Voronoi polygon as the moving target position. The performance evaluation shows that the proposed scheme achieves better results than the existing schemes in terms of fast coverage expansion.

Inspired from natural self-managing behavior of the human body, autonomic systems promise to inject self-managing behavior in software systems. Such behavior enables self-configuration, self-healing, self-optimization and self-protection capabilities in software systems. Self-configuration is required in systems where efficiency is the key issue, such as real time execution environments. To solve self-configuration problems in autonomic systems, the use of various problem-solving techniques has been reported in the literature including case-based reasoning. The case-based reasoning approach exploits past experience that can be helpful in achieving autonomic capabilities. The learning process improves as more experience is added in the case-base in the form of cases. This results in a larger case-base. A larger case-base reduces the efficiency in terms of computational cost. To overcome this efficiency problem, this paper suggests to cluster the case-base, subsequent to find the solution of the reported problem. This approach reduces the search complexity by confining a new case to a relevant cluster in the case-base. Clustering the case-base is a one-time process and does not need to be repeated regularly. The proposed approach presented in this paper has been outlined in the form of a new clustered CBR framework. The proposed framework has been evaluated on a simulation of Autonomic Forest Fire Application (AFFA). This paper presents an outline of the simulated AFFA and results on three different clustering algorithms for clustering the case-base in the proposed framework. The comparison of performance of the conventional CBR approach and clustered CBR approach has been presented in terms of their Accuracy, Recall and Precision (ARP) and computational efficiency.

The exact time complexity of Hsu and Huan's self-stabilizing maximal matching algorithm is provided. It is n2 + n - 2 if the number of nodes n is even and n2 + n - if n is odd.

This paper proposes a self-taught classifier of gateways for hybrid SLAM. Gateways are detected and recognized by the self-taught classifier, which is a SVM classifier and self-taught in that its training samples are produced and labeled without user's intervention. Since the detection of gateways at the topological boundaries of an acquired metric map reduces computational complexity in partitioning the metric map into sub-maps as compared with previous hybrid SLAM approaches using spectral clustering methods, from O(2n) to O(n), where n is the number of sub-maps. This makes possible real time hybrid SLAM even for large-scale metric maps. We have confirmed that the self-taught classifier provides satisfactory consistency and computationally efficiency in hybrid SLAM through different experiments.

This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.

We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.

We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12 bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2 Mλ2 area with 35 bits of SRAM, and the prototype SSFPGA with 3430 (1020) blocks is designed and fabricated using 65 nm CMOS. Measured results show at 1.2 V 430 MHz and 647 MHz operation for a 3 bit ripple carry adder, without and with throughput optimization, respectively. We find that using the proposed pipeline alignment techniques we can perform at maximum throughput of 647 MHz in various benchmarks on the SSFPGA. We demonstrate up to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

An inter-modulation distortion (IMD) compensation method for thermal memory effect using a multistage RC-ladder circuit has been proposed. The IMD caused by the thermal memory effect on an InGaP/GaAs HBT amplifier was compensated for by inserting a multistage RC-ladder circuit in the base bias circuit of the amplifier. Since heat flux owing to self-heating in the transistor can be approximated with a multistage thermal RC-ladder circuit, the canceling of IMD by an additional electrical memory effect generated from the RC-ladder circuit is predicted. The memory effects cause asymmetrical characteristics between upper and lower IMD. The IMD caused by the memory effects is expressed as a vector sum of each origin. By adjusting an electrical reactance characteristic for sub-harmonics affected by the thermal memory effect in the amplifier circuit, the asymmetric characteristic is symmetrized. The parameters of the RC-ladder circuit were estimated so that the adjusted electrical reactance characteristic is reproduced in simulation. A fabricated InGaP/GaAs HBT amplifier with the thermal memory effect compensation circuit exhibited a symmetrized and suppressed IMD characteristics.

In this study, a new scanning method for measuring field distributions is proposed. In this method, measurement positions are automatically decided by a magnetic tracker. This method obtains field distributions in real-time, and can display field distribution map successively by interpolating.