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[Keyword] ERG(867hit)

741-760hit(867hit)

  • Analysis on Convergence Property of INLMS Algorithm Suitable for Fixed Point Processing

    Kensaku FUJII  Juro OHGA  

     
    PAPER-Adaptive Signal Processing

      Vol:
    E83-A No:8
      Page(s):
    1539-1544

    The individually normalized least mean square (INLMS) algorithm is proposed as an adaptive algorithm suitable for the fixed point processing. The convergence property of the INLMS algorithm, however, is not yet analyzed enough. This paper first derives an equation describing the convergence property by exploiting the technique of expressing the INLMS algorithm as a first order infinite impulse response (IIR) filter. According to the equation derived thus, the decreasing process of the estimation error is represented as the response of another IIR filter expression. By using the representation, this paper second derives the convergence condition of the INLMS algorithm as the range of the step size making a low path filter of the latter IIR filter. This paper also derives the step size maximizing the convergence speed as the maximum coefficient of the latter IIR filter and finally clarifies the range of the step size recommended in the practical system design.

  • Studies on the Convergence Speed of Over-Sampled Subband Adaptive Digital Filters

    Shuichi OHNO  

     
    PAPER-Adaptive Signal Processing

      Vol:
    E83-A No:8
      Page(s):
    1531-1538

    To evaluate or compare the convergence speed of adaptive digital filters (ADF) with least mean squared (LMS) algorithm, the condition numbers of correlation matrices of tap-input vectors are often used. In this paper, however, the comparison of the conventional fullband ADF and the subband ADF based on their condition numbers is shown to be invalid. In some cases, the over-sampled subband ADF converges faster than the fullband ADF, although the former has larger condition numbers. To explain the above phenomenon, an expression for the convergence behavior of the subband ADF and simulation results are provided.

  • Energy Level Alignment and Band Bending at TPD/Metal Interfaces Studied by Kelvin Probe Method

    Naoki HAYASHI  Eisuke ITO  Hisao ISHII  Yukio OUCHI  Kazuhiko SEKI  

     
    LETTER-Electro Luminescence

      Vol:
    E83-C No:7
      Page(s):
    1009-1011

    In order to examine the validity of Mott-Schottky model at organic/metal interfaces, the position of the vacuum level of N,N'-bis(3-methylphenyl)-N,N'-diphenyl -[1,1'-biphenyl]-4,4'-diamine (TPD) film formed on various metal substrates (Au, Cu, Ag, Mg and Ca) was measured as a function of the film-thickness by Kelvin probe method in ultrahigh vacuum (UHV). TPD is a typical hole-injecting material for organic electroluminescent devices. At all the interfaces, sharp shifts of the vacuum level were observed within 1 nm thickness. Further deposition of TPD up to 100 nm did not change the position of the vacuum level indicating no band bending at these interfaces. These findings clearly demonstrate the Fermi level alignment between metal and bulk TPD solid is not established within typical thickness of real devices.

  • Load Leveling Using EDLCs under PLL Control

    Goichi ARIYOSHI  Katsuaki MURATA  Koosuke HARADA  Kiyomi YAMASAKI  

     
    PAPER

      Vol:
    E83-A No:6
      Page(s):
    1014-1022

    Demand for power in Japan has been increasing year by year, and steep demand is projected during daily peak load periods: particularly in summer, due to growing demand for air conditioning. This has resulted in a large gap between day and night demand for power. The daily and seasonal regularity of this demand gap is placing pressure on power utilities to reduce service costs and create a more dependable power supply. This study demonstrates the feasibility of an energy storage system for load leveling based on the electric double-layer capacitor (EDLC). This device is safer, has a longer service life and needs far less maintenance than the secondary cell. The system works to store surplus energy from a commercial AC line in an EDLC bank during the night, and release this energy for use during the daytime peak load period, using a novel interface circuit. This paper focuses in particular on the working principles and experimental results of the interface circuit, which comprises a voltage control oscillator (VCO), a bi-directional DC/DC converter, a bi- directional inverter, and a coupling inductor. The whole circuit is subjected to PLL control, so that automatic connection between DC from an EDLC bank and AC from a commercial power line may take place in a simpler, more reliable and less costly manner. The system allows for energy transfer on the basis of DC voltage as if electric charging and discharging had taken place in a full DC system.

  • Design Pattern Applying Support OOPAS by Design Diagram Merging

    Minoru HARADA  Hidetsugu NAGAYAMA  

     
    PAPER-Software Systems

      Vol:
    E83-D No:6
      Page(s):
    1237-1244

    Design patterns which Erich Gamma advocates is expected as an effective approach for the reuse of designs. So, design patterns are predicted to be used frequently in object-oriented software development. In such circumstance, tools to support applying design patterns to the design diagrams of the system under development are thought to be useful. This research develops Object-Oriented Pattern Applying Support tool OOPAS. It consists of a library of Gamma design patterns with very familiar examples and adrem explanation, and of a function to generate the correctly modified design diagrams of the application system when a design pattern was applied to evolve that system. Actually, these functions are installed in the structured object modeling environment SOME, which is an object-oriented design diagram editor made previously in our laboratory. This design diagram evolving function is formalized as a Join operation of the recursive graph. As a result of the evaluation experiment, the join operation can be applied to the almost of the twenty three Gamma design patterns excluding the six patterns such as Iterator and Command, which are stated at too abstract level to be represented by the design diagrams.

  • Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs

    Koji INOUE  Koji KAI  Kazuaki MURAKAMI  

     
    PAPER-Computer System Element

      Vol:
    E83-D No:5
      Page(s):
    1048-1057

    This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache). " The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory-access time improvement achieved by a direct-mapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with fixed 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache.

  • A Circularly Connected Synergetic Neural Network

    Masahiro NAKAGAWA  

     
    PAPER-Neural Networks and Bioengineering

      Vol:
    E83-A No:5
      Page(s):
    909-922

    In this paper we shall put forward a novel circularly connected synergetic neural network extending the previously studied auto-correlation or cross-correlation dynamics so as to realise a group memory retrieval. The present model is substantially based on a top-down approach of the dynamic rule of an analog neural network in the similar manner to the conventional synergetic dynamics early proposed by Haken. It will be proved that a complete association can be assured up to the same number of the embedded patterns as the minimal number of neurons of the linked synergetic neural networks. In addition, one finds that a searching process of a couple of embedded patterns can be also realised by means of controlling attraction parameters as was previously reported in the autoassociative synergetic models.

  • Crystalline and Optical Properties of ELO GaN by HVPE Using Tungsten Mask

    Kazumasa HIRAMATSU  Atsushi MOTOGAITO  Hideto MIYAKE  Yoshiaki HONDA  Yasushi IYECHIKA  Takayoshi MAEDA  Frank BERTRAM  Juergen CHRISTEN  Axel HOFFMANN  

     
    INVITED PAPER

      Vol:
    E83-C No:4
      Page(s):
    620-626

    The epitaxial lateral overgrowth (ELO) of GaN with a stripe tungsten (W) mask pattern is performed by hydride vapor phase epitaxy (HVPE) and the crystalline and optical properties are investigated compared with ELO GaN using SiO2 mask by characterizations of X-ray rocking curve (XRC), transmission electron microscopy (TEM) and low temperature cathodoluminescence (CL). A buried ELO structure of the W mask with a smooth surface is successfully obtained. The tilt of c-axis on the W mask in the ELO GaN is not observed, but in the case of the SiO2 mask, c-axis tilts on the mask region at 1 to 10 together with small angle grain boundaries. Half the way from the ELO interface to the surface, the luminescence becomes excitonic over the whole lateral extension region, which indicates the optically high crystalline quality of the material. On the other hand, different kinds of luminescence are observed depending on the position. The difference of these luminescence is caused by the defects and/or impurity incorporation on the mask region due to the tilting of c-axis.

  • Minimum Number of Comparators in (6,6)-Merging Network

    Koichi YAMAZAKI  Hibiki MIZUNO  Kazuhisa MASUDA  Shigeki IWATA  

     
    PAPER-Theory/Models of Computation

      Vol:
    E83-D No:2
      Page(s):
    137-141

    The minimum number of comparators in a (6,6)-merging network is shown to be 17. The number has been known to be either 16 or 17 [See Knuth, The Art of Computer Programming Vol. 3: Sorting and Searching, p. 230]. Minimum numbers for (n,n)-merging netwerks, 1 n 9, n 6, were already known. The problem had been open for more than two decades.

  • A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection

    Koji INOUE  Tohru ISHIHARA  Kazuaki MURAKAMI  

     
    PAPER

      Vol:
    E83-C No:2
      Page(s):
    186-194

    This paper proposes a new approach to achieving high performance and low energy consumption for set-associative caches. The cache, called way-predicting set-associative cache, speculatively selects a single way, which is likely to contain the data desired by the processor, from the set designated by a memory address, before it starts a normal cache access. By accessing only the single way predicted, instead of accessing all the ways in a set, energy consumption can be reduced. In order for the way-predicting cache to perform well, accuracy of way prediction is important. This paper shows that the accuracy of an MRU (most recently used)-based way prediction is higher than 90% for most of the benchmark programs. The proposed way-predicting cache improves the ED (energy-delay) product by 60-70% compared to the conventional set-associative cache.

  • Underground Pipe Signal Extraction Using LoG Filter from Pulse Radar Images

    Mitsushige OKADA  Toru KANEKO  Kenjiro T. MIURA  

     
    LETTER-Image Processing, Image Pattern Recognition

      Vol:
    E83-D No:1
      Page(s):
    112-115

    A method for locating underground pipes from a pulse radar image is presented. The method employs the Laplacian of Gaussian filter to extract edges and employs the Hough transform to determine the depth of the pipes. A preliminary experiment showed its ability to detect deeply buried pipes with weak signal echoes.

  • Chip-by-Chip Turbo Coding for DS/SS Systems

    Chen ZHENG  Takaya YAMAZATO  Masaaki KATAYAMA  Akira OGAWA  

     
    PAPER

      Vol:
    E82-A No:12
      Page(s):
    2751-2757

    Most of error correcting codes applying to DS/SS systems are such that information data is first (bit-by-bit) encoded and then spread by pseudo noise (PN) sequence. Thus, coding gain achieved by such systems are mainly due to the error correcting codes and the redundancy produced by the spreading codes shows no effect on the coding gain. In this paper, a chip-by-chip Turbo coding for DS/SS systems is proposed. The input information data is first spread by PN sequence and then fed into the Turbo-encoder which operates in chip timing. As the Turbo-encoder operates in chip timing, a large interleaving size would be obtained, which improves the performance. As results, superior performances with coding gain of more than 3.0 dB and 5.0 dB for AWGN and Rayleigh-fading channel, respectively, were found with short frame size of information data.

  • Schedule-Clock-Tree Routing for Semi-Synchronous Circuits

    Kazunori INOUE  Wataru TAKAHASHI  Atsushi TAKAHASHI  Yoji KAJITANI  

     
    PAPER

      Vol:
    E82-A No:11
      Page(s):
    2431-2439

    It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.

  • An Evaluation of Visual Fatigue in 3-D Displays: Focusing on the Mismatching of Convergence and Accommodation

    Toshiaki SUGIHARA  Tsutomu MIYASATO  Ryohei NAKATSU  

     
    PAPER

      Vol:
    E82-C No:10
      Page(s):
    1814-1822

    In this paper, we describe an experimental evaluation of visual fatigue in a binocular disparity type 3-D display system. To evaluate this fatigue, we use a subjective assessment method and focus on mismatching between convergence and accommodation, which is a major weakness of binocular disparity 3-D displays. For this subjective assessment, we use a newly-developed binocular disparity 3-D display system with a compensation function for accommodation. Because this equipment only allowed us to compare the terms of the mismatching itself, the evaluation is more accurate than similar previous works.

  • A Study on Performances of Soft-Decision Decoding Algorithm Based on Energy Minimization Principle

    Akira SHIOZAKI  Yasushi NOGAWA  Tomokazu SATO  

     
    LETTER-Coding Theory

      Vol:
    E82-A No:10
      Page(s):
    2194-2198

    We proposed a soft-decision decoding algorithm for cyclic codes based on energy minimization principle. This letter presents the algorithm which improves decoding performance and decoding complexity of the previous method by giving more initial positions and introducing a new criterion for terminating the decoding procedure. Computer simulation results show that both the decoded block error rate and the decoding complexity decrease by this method more than by the previous method.

  • Analysis of Modified Luneberg Lens Using Exact Solutions

    Haruo SAKURAI  Makoto OHKI  Shogo KOZAKI  

     
    PAPER-Electromagnetic Theory

      Vol:
    E82-C No:10
      Page(s):
    1846-1852

    Analytical solutions have been obtained for the electromagnetic scattering by a modified Luneberg lens with the permittivity of arbitrary parabolic function. They are expressed by four spherical vector wave functions for radially stratified medium which were introduced for the Luneberg lens by C. T. Tai. They consist of the confluent hypergeometric function and a "generalized" confluent hypergeometric function, in which the parameters for the permittivity of arbitrary parabolic function are involved. The characteristics of the modified Luneberg lens are numerically investigated using exact solutions in comparison with that of the conventional Luneberg lens. The bistatic cross section, the forward cross section and the radar cross section are studied in detail. The near-field distribution is also investigated in order to study the focal properties of the Luneberg lens. The focal shifts defined by the distance between the geometrical focal point and the electromagnetic focal point are obtained for various ka (k is the wave number and a is the radius of the lens). The focal shift normalized to the radius of the sphere becomes larger as ka is smaller. However it drops down rapidly for ka5 when the peak of the electric field amplitude appears on the surface of sphere.

  • A Synergetic Approach to Speculative Price Volatility

    Taisei KAIZOJI  

     
    PAPER

      Vol:
    E82-A No:9
      Page(s):
    1874-1882

    In this paper we propose a heterogeneous agents model that represents speculative dynamics by using the synergetic approach. We consider the markets for three securities (a stock, a bond, and a foreign currency). Each market consists of two typical types of investors: fundamentalists and bandwagon traders. We show the characteristic patterns of speculative prices (speculative bubbles and speculative chaos) which are generated by trading between the fundamentalists and bandwagon traders.

  • Relation between the Stored and the Dissipated Energies of a Circuit Composed of Linear Capacitors, Linear/Nonlinear Resistors and dc Voltage Sources

    Yutaka JITSUMATSU  Tetsuo NISHI  

     
    PAPER

      Vol:
    E82-A No:9
      Page(s):
    1802-1808

    We consider a circuit composed of linear capacitors, nonlinear resistors, and dc voltage sources and show the possibility that the total energy dissipated at resistors in the above circuit is smaller than the energy stored at capacitors. Linear passive circuits cannot possess such a property.

  • Efficient Image Segmentation Preserving Semantic Object Shapes

    Hyun Sang PARK  Jong Beom RA  

     
    PAPER

      Vol:
    E82-A No:6
      Page(s):
    879-886

    Homogeneous but distinct visual objects having low-contrast boundaries are usually merged in most of the segmentation algorithms. To alleviate this problem, an efficient image segmentation algorithm based on a bottom-up approach is proposed by using spatial domain information only. For initial image segmentation, we adopt a new marker extraction algorithm conforming to the human visual system. It generates dense markers in visually complex areas and sparse markers in visually homogeneous areas. Then, two region-merging algorithms are successively applied so that homogeneous visual objects can be represented as simple as possible without destroying low-contrast real boundaries among them. The first one is to remove insignificant regions in a proper merging order. And the second one merges only homogeneous regions, based on ternary region classification. The resultant segmentation describes homogeneous visual objects with few regions while preserving semantic object shapes well. Finally, a size-based region decision procedure may be applied to represent complex visual objects simpler, if their precise semantic contents are not necessary. Experimental results show that the proposed image segmentation algorithm represents homogeneous visual objects with a few regions and describes complex visual objects with a marginal number of regions with well-preserved semantic object shapes.

  • Reversible Energy Recovery Logic Circuits and Its 8-Phase Clocked Power Generator for Ultra-Low-Power Applications

    Joonho LIM  Dong-Gyu KIM  Soo-Ik CHAE  

     
    PAPER-Integrated Electronics

      Vol:
    E82-C No:4
      Page(s):
    646-653

    We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme, which is a dual-rail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-µm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal.

741-760hit(867hit)