This paper presents an efficient heuristic algorithm for min-cut bisection of weighted hypergraphs. The proposed algorithm is based on a heuristic algorithm proposed by Kahng, which was devised for non-weighted hypergraph bisection, adopting a non-weighted graph called intersection graph to represent a given hypergraph. In the proposed algorithm, instead of an intersection graph, a bipartite graph called netgraph is newly introduced to explicitly represent the weights of nodes of a hypergraph. Using the netgraph, it is easy to partition a weighted hypergraph into two hypergraphs with same size. Computation time of the proposed method is O(m2), where m is the number of nodes of a given hypergraph. Experimental results with real circuit data show that the proposed method produces better solutions in shorter computation time compared with existing methods.

Most communication cables are laid underground. In order to make construction and maintenance works easier, systems to detect buried objects have already been developed using the electromagnetic pulse radar technique. However, existing detection systems are not really practical due to their rather limited processing speed. To achieve sufficient processing speed, two dedicated custom FFT LSI's are designed and realized with 0.8 µm-CMOS technology. The two chips have an equivalent processing capacity of 200 MOPS. An efficietn hardware algorithm for address generation and 2 word parallel processing are introduced. In addition, an enhanced system organization is developed together with an improved pattern recognition scheme and aperture synthesis hardware. The new processor executes a FFT/parameter extraction operation in 4 seconds and aperture synthesis in 1 second. This speed meets the design target, and a real time detection system for underground objects becomes possible.

Thin Si films grown on anodized porous silicon have been characterized using a high-energy ion scattering technique with related simulations of MeV ions in solids. It turned out that the simulations are necessary and very usuful for quantitative and nondestractive analysis of thin films with thicknesses less than 100 nm. In the case of the epitaxial Si films examined, it is often insufficient for the characterization of crystalline quality to measure only the channeling minimum yield, and therefore, it is emphasized that angular scans over the critical angle in the vicinity of a channeling direction must be performed for the analysis of possible imperfections in thin films. The possible imperfections observed in the epitaxial specimen are treated quantitatively.

In this paper the three dimensional (3-D) effect on CMOS latch-up is modeled using a graphical technique based on the fundamental principle of "charge neutrality or its current continuity equivalent" in the base region of parasitic transistors involved in latch-up. The graphical generation of the complete latch-up I-V characteristic requires as an input the SPICE parameters of the relevant bipolar and MOS transistors, the values of shunt resistances and the reverse current-voltage characteristic of the well-substrate junction. The infiuence of the MOS transistor shunting the parasitic bipolar transistors has received special attention. The nonideal scaling of the parasitic resistances has been observed to be the most crucial parameter determining the 3-D nature of the device. The proposed model is validated with test-structures fabricated in 2 µm bulk CMOS technology at and above room temperature. SAFE space map is constructed with width W as a parameter.

The inherent simplicity of the LMS (Least Mean Square) Algorithm has lead to its wide usage. However, it is well known that high speed convergence and low final misadjustment cannot be realized simultaneously by the conventional LMS method. To overcome this trade-off problem, a new adaptive algorithm using Multiple ADF's (Adaptive Digital Filters) is proposed. The proposed algorithm modifies coefficients using multiple gradient vectors of the squared error, which are computed at different points on the performance surface. First, the proposed algorithm using 2 ADF's is discussed. Simulation results show that both high speed convergence and low final misadjustment can be realized. The computation time of this proposed algorithm is nearly as much as that of LMS if parallel processing techniques are used. Moreover, the proposed algorithm using more than 2 ADF's is discussed. It is understood that if more than 2 ADF's are used, further improvement in the convergence speed in not realized, but a reduction of the final misadjustment and an improvement in the stability are realized. Finally, a method which can improve the convergence property in the presence of correlated input is discussed. It is indicated that using priori knowledge and matrix transformation, the convergence property is quite improved even when a strongly correlated signal input is applied.

The two most important parameters in reactive ion etching process, ion bombardment energy and flux, were extracted through a simple RF waveform measurement at the excitation electrode in a conventional cathode-coupled plasma RIE system. By using the extracted plasma parameters, damage and contamination in Si substrates induced by reactive ion etching in a SiCl4 plasma were investigated. A very convenient map representation of ion energy and ion flux was introduced in understanding the etching process occurring in the RIE system.

A spherical-harmonics expansion method is used to find approximate numerical solutions of the Boltzmann Transport Equation in the homogeneous case. Acoustic and optical phonon scattering, ionized impurity scattering as well as an energy band structure fitting the silicon density of states up to 2.6 eV above the conduction-band edge are used in the model. Comparisons with Monte Carlo data show excellent agreement, and prove that detailed information on the high-energy tail of the distribution function can be obtained at very low cost using this methodology.