A new method using new test structure, which is connected 15.4 million MOS transistor, for evaluating extrinsic oxide breakdown is proposed. The active gate area which is needed to predict reliability will be shown. And by using this new method, activation energy not only for the intrinsic breakdown but also for the extrinsic breakdown are obtained.

This paper proposes a traffic-adaptive dynamic routing method, which we have named RAG, for connectionless packet networks. Conventional traffic control methods discard the packets which cause congestion. Furthermore, conventional routing methods propagate control messages all over the network for gathering global topology information, and this causes more congestion. In contrast, RAG estimates traffic conditions all over a network without any communication between nodes and makes the best use of free links so that packets make detours to avoid congestive sites. RAG adopts distributed control based on game theory (non-communication, non-zero-sum, two-person). With RAG, nodes play a packet-forwarding game without any communication with each other, and each node controls ordering and routing of the forwarding packets based on the node's individual payoff table which is dynamically reconstructed by observation of surrounding nodes. Nodes cooperate with each other, except for punishment for disloyalty. Repetition of these local operations in nodes aims at the emergence of the gradual network-global traffic balancing. The results of experiments in comparison with the conventional shortest path first (SPF) routing method show that the throughput is about 1.58 times higher with the new method.

The pseudo-inverse model for the associative memory has an iterative algorithm converging to its weight matrix. The present letter shows that the same algorithm except for the lack of self couplings can be derived by simple consideration of the energy of the network state.

Epsilon serializability (ESR) was proposed to relax serializability constraints by allowing transactions to execute with a limited amount of inconsistency (ε-spec). Divergence control algorithms, viewed as extensions of concurrency control algorithms, enable read-only transactions to complete if their inconsistencies do not exceed ε-spec. This paper studies the performance of two-phase locking divergence control (2PLDC) and optimistic divergence control (ODC) algorithms. We develop a central part of the ESR transaction processing system that runs with 2PLDC and ODC. We applied a comprehensive centralized database simulation model to measure the performance. Evaluations are conducted with multi-class workloads where on-line update transactions and long-duration queries progress under various ε-spec. Our results demonstrate that significant performance enhancements are achieved with a non-zero tolerable inconsistency. With sufficient ε-spec and limited system resources, both algorithms result in comparable performance. However, with low resource contention, ODC performs significantly better than 2PLDC. Furthermore, in the range of small ε-spec, the queries committed by ODC have more accurate results than those committed by 2PLDC.

A fractal image coding scheme using classified range regions is proposed. Two classes of range regions, shade and nonshade, are defined here, A shade range region is encoded by the average gray level, while a nonshade range region is encoded by IFS parameters. To obtain classified range regions, the two-stage block merging scheme is proposed. Each range region is produced by merging primitive square blocks. Shade range regions are obtained at the first stage, and from the rest of primitive blocks nonshade range regions are obtained at the second stage. Furthermore, for increasing the variety of region shape, the 8-directional block merging scheme is defined by extension of the 4-directional scheme. Also, two similar schemes for encoding region shapes, each corresponding to the 4-directional block merging scheme and the 8-directional block merging scheme, are proposed. From the results of simulation by using a test image, it was demonstrated that the variety of region shape allows large shade range regions to be extracted efficiently, and these large shade range regions are more effective in reduction of total amount of codebits with less increase of degradation of reconstructed image quality than large nonshade range regions. The 8-directional merging and coding scheme and the 4-directional scheme reveal almost the same coding performance, which is improved than that of the quad-tree partitioning scheme. Also, these two schemes achieve almost the same reconstructed image quality.

A double-layer Associative Memory System (AMS) based on the Cerebella Model Articulation Controller (CMAC) (CMAC-AMS), owing to its advantages of simple structures, fast searching procedures and strong mapping capability between multidimensional input/output vectors, has been successfully used in such applications as real-time intelligent control, signal processing and pattern recognition. However, it is still suffering from its requirement for a large memory size and relatively low precision. Furthermore, the hash code used in its addressing mechanism for memory size reduction can cause a data-collision problem. In this paper, a new high-order Associative Memory System based on the Newton's forward interpolation formula (NFI-AMS) is proposed. The NFI-AMS is capable of implementing high-precision approximation to multivariable functions with arbitrarily given sampling data. A learning algorithm and a convergence theorem of the NFI-AMS are proposed. The network structure and the scheme of its learning algorithm reveal that the NFI-AMS has advantages over the conventional CMAC-type AMS in terms of high precision of learning, much less required memory size without the data-collision problem, and also has advantages over the multilayer Back Propagation (BP) neural networks in terms of much less computational effort for learning and fast convergence rate. Numerical simulations verify these advantages. The proposed NFI-AMS, therefore, has potential in many application areas as a new kind of associative memory system.

A highly reliable and highly efficient fuel-cell energy system is being developed that can run on various fuels and is suitable for a cogeneration system for telecommunications facilities. In this system, electrical power supplants the mains power and heat energy is used for air conditioning. Using this fuel-cell power plant as an emergency generator and ensuring the reliability of telecommunications requires the use of alternate fuels. This plant can run on liquefied petroleum gas(LPG)if the pipeline gas supply stops. Fuel substitution characteristics, and DC and AC interconnection characteristics have been experimentally demonstrated for connections by using a 200-kW phosphoric acid fuel cell and a 150-kW engine generator.

We propose a novel soft-decision decoding algorithm for cyclic codes based on energy minimization principle. The well-known soft-decision decoding algorithms for block codes perform algebraic (hard-decision) decoding several times in order to generate candidate codewords using the reliability of received symbols. In contrast, the proposed method defines energy as the Euclidean distance between the received signal and a codeword and alters the values of information symbols so as to decrease the energy in order to seek the codeword of minimum energy, which is the most likely codeword. We let initial positions be the information parts of signals obtained by cyclically shifting a received signal and look for the point, which represents a codeword, of minimum energy by moving each point from several initial positions. This paper presents and investigates reducing complexity of the soft-decision decoding algorithm. We rank initial positions in order of reliability and reduce the number of initial positions in decoding. Computer simulation results show that this method reduces decoding complexity.

In this paper the performance of the Block Sorting algorithm proposed by Burrows and Wheeler is evaluated theoretically. It is proved that the Block Sorting algorithm is asymptotically optimal for stationary ergodic finite order Markov sources. Our proof is based on the facts that symbols with the same Markov state (or context) in an original data sequence are grouped together in the output sequence obtained by Burrows-Wheeler transform, and the codeword length of each group can be bounded by a function described with the frequencies of symbols included in the group.

In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.

Computational expensiveness of the training techniques, due to the extensiveness of the data set, is among the most important factors in machine learning and neural networks. Oversized data set may cause rank-deficiencies of Jacobean matrix which plays essential role in training techniques. Then the training becomes not only computationally expensive but also ineffective. In [1] the authors introduced the theoretical grounds for dynamic sample selection having a potential of eliminating rank-deficiencies. This study addresses the implementation issues of the dynamic sample selection based on the theoretical material presented in [1]. The authors propose a sample selection algorithm implementable into an arbitrary optimization technique. An ability of the algorithm to select a proper set of samples at each iteration of the training has been observed to be very beneficial as indicated by several experiments. Recently proposed approaches to sample selection work reasonably well if pattern-weight ratio is close to 1. Small improvements can be detected also at the values of the pattern-weight ratio equal to 2 or 3. The dynamic sample selection approach, presented in this article, can increase the convergence speed of first order optimization techniques, used for training MLP networks, even at the value of the pattern-weight ratio (E-FP) as high as 15 and possibly even more.

Conventional approaches to neural network training do not consider possibility of selecting training samples dynamically during the learning phase. Neural network is simply presented with the complete training set at each iteration of the learning. The learning can then become very costly for large data sets. Huge redundancy of data samples may lead to the ill-conditioned training problem. Ill-conditioning during the training causes rank-deficiencies of error and Jacobean matrices, which results in slower convergence speed, or in the worst case, the failure of the algorithm to progress. Rank-deficiencies of essential matrices can be avoided by an appropriate selection of training exemplars at each iteration of training. This article presents underlying theoretical grounds for dynamic sample selection (DSS), that is mechanism enabling to select a subset of training set at each iteration. Theoretical material is first presented for general objective functions, and then for the objective functions satisfying the Lipschitz continuity condition. Furthermore, implementation specifics of DSS to first order line search techniques are theoretically described.

In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. In order to reconsider the DRAM data retention characteristics, this paper formulates and evaluates the performance degradation due to conflicts between normal DRAM accesses and refresh operations. Next, this paper proposes a new DRAM refresh architecture which intends to reduce unnecessary refreshes. This architecture exploits multiple refresh periods. Each row is refreshed with the most appropriate period of them. Reducing the number of refreshes improves the accessibility to DRAM. It is shown that the method reduces the number of refreshes and the degree of the performance degradation of the logic portion.

Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy including cache memory, we can exploit such high on-chip memory bandwidth by means of replacing a whole cache line (or cache block) at a time on cache misses. This approach tends to increase the cache-line size if we attempt to improve the attainable memory bandwidth. Larger cache lines, however, might worsen the system performance if programs running on the LSIs do not have enough spatial locality of references and cache misses frequently take place. This paper describes a novel cache architecture suitable for merged DRAM/logic LSIs, called variable line-size cache or VLS cache, for resolving the above-mentioned dilemma. The VLS cache can make good use of the high on-chip memory bandwidth by means of larger cache lines and, at the same time, alleviate the negative effects of larger cache-line size by partitioning each large cache line into multiple sub-lines and allowing every sub-line to work as an independent cache line. The number of sub-lines involved when a cache replacement occurs can be determined depending on the characteristics of programs. This paper also evaluates the cost/performance improvements attainable by the VLS cache and compares it with those of conventional cache architectures. As a result, it is observed that a VLS cache reduces the average memory-access time by 16. 4% while it increases the hardware cost by only 13%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

The electromagnetic interference (EMI) induced by steady arc has been demonstrated to be dependent on arc voltage fluctuation when the arc transfers from the metallic phase to the gaseous phase. In order to give the physical understanding of this arc voltage fluctuation and EMI, several typical materials, such as Ag, Cu and Zr, were tested and their arc behavior was determined and compared. The experimental results indicated that the arc behavior, in particular the arc voltage fluctuation in the moment that metallic phase transfers to the gaseous phase was different for different materials. Based on the test results and former investigations, a plausible mechanism is proposed for understanding these phenomena.

In this paper, three issues concerning the linear adaptive receiver using the LMS algorithm for single-user demodulation in direct-sequence/code-division multiple-access (DS/CDMA) systems are considered. First, the convergence rate of the LMS algorithm in DS/CDMA environment is considered theoretically. Both upper and lower bounds of the eigenvalue spread of the autocorrelation matrix of receiver input signals are derived. It is cleared from the results that the convergence rate of the LMS algorithm becomes slow when the signal power of interferer is large. Second, fast converging technique using a prefilter is considered. The LMS based adaptive receiver using an adaptive prefilter adjusted by a Hebbian learning algorithm to decorrelate the input signals is proposed. Computer simulation results show that the proposed receiver provides faster convergence than the LMS based receiver. Third, the complexity reduction of the proposed receiver by prefiltering is considered. As for the reduced complexity receiver, it is shown that the performance degradation is little as compared with the full complexity receiver.

Let {Xk}k=- be a stationary and ergodic information source, where each Xk takes values in a standard alphabet A with a distance function d: A A [0, ) defined on it. For each sample sequence X = (, x-1, x0, x1, ) and D > 0 let the approximate D-match recurrence time be defined by Rn (x, D) = min {m n: dn (Xn1, Xm+nm+1) D}, where Xji denotes the string xixi+1 xj and dn: An An [0, ) is a metric of An induced by d for each n. Let R (D) be the rate distortion function of the source {Xk}k=- relative to the fidelity criterion {dn}. Then it is shown that lim supn-1/n log Rn (X, D) R (D/2) a. s.

We have developed a Beam Space CMA (Constant Modulus Algorithm) Adaptive Array Antenna system (BSCMA adaptive array antenna) that may be suitable for mobile communications. In this paper, we present experimental results of interference cancellation characteristics using the developed system. The experiment was carried out in a large radio anechoic chamber, while desired and interference signals were transmitted to the system. We focused on the characteristics of capture, convergence and tracking in adaptive processing. The experimental results show excellent interference cancellation characteristics, and demonstrate that the BSCMA adaptive array antenna has a greater feasibility to be applied practically in mobile communications.

In this paper, we discuss an emergent behavior of a multi-elevator system. The system includes multiple elevators in an office building and the Poisson arrival of passengers as its input. Elevators move up and down to serve calls and carry passengers according to given working rules. The system is a representative discrete event dynamic system, and is a nonlinear complex system. When people leave a building at the closing time, the down-peak traffic of passengers occurs. We show numerically that (1) this causes a jamming effect, which reduces the transportation efficiency, (2) there exists a threshold in the arrival rate of passengers, at which the traffic rate starts decreasing, and (3) this jamming effect is due to the synchronization of elevators. Then we propose a dispatching control that prevents elevators from synchronizing. This control is applied to each elevator as an anxiliary working rule. We can remove the jamming effect and recover the transportation efficiency by the control.

In this letter, the absolute exponential stability result of neural networks with asymmetric connection matrices is obtained, which generalizes the existing one about absolute stability of neural networks, by a new proof approach. It is demonstrated that the network time constant is inversely proportional to the global exponential convergence rate of the network trajectories to the unique equilibrium. A numerical simulation example is also given to illustrate the obtained analysis results.