When orignal signals are contaminated by both additive and signal-dependent noise components, the test statistics of locally optimum detector are obtained for detection of weak composite signals based on the generalized Neyman-Pearson lemma. In order to consider the non-additive noise as well as purely-additive noise, a generalized observation model is used in this paper. The locally optimum detector test statisics are derived for all different cases according to the relative strengths of the known signal, random signal, and signal-dependent noise components. Schematic diagrams of the structures of the locally optimum detector are also included. The finite sample-size performance characteristics of the locally optimum detector are compared with those of other common detectors.

The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the deisrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then u is the expected unit time.

To derive blood flow dynamics from cineangiograms (CAG), we have developed an image processing algorithm to estimate a two-dimensional blood fiow velocity map projected on CAG. Each image area of CAG is diveded into blocks, and it is assumed that the movement of the contrast medium between two serial frames is restricted only to adjacent blocks. By this assumption, a fundamental equation" and the maximum flow constraints" are derived. The equation and constraints state the relationship between the volume of contrast medium in each block and the flow components" that are the volumes of contrast medium flowing from/to its adjacent blocks. The initial guess" that is a set of approximately obtained flow components is corrected using these relationships. The corrected flow components are then transformed into blood flow velocities, which are illustrated in the form of a needle diagram. In numerical experiments, the estimation error between the real flow velocity generated artificially and the flow velocity estimated with our algorithm was evaluated under one of the worst conditions. Although the maximum error was fairly large, the estimated flow velocity map was still acceptable for visual inspection of flow velocity pattern. We then applied our algorithm to an abdominal CAG (clinical data). The results showed flow stagnation and reverse flow in the abdominal aneurysm, which are consistent with the presence of a thrombus in the aneurysm. This algorithm may be a useful diagnostic tool in the assessment of vascular disease.

This paper proposes a scheme that offers robust extraction of target images in standard view from input facial images, in order to realize accurate and automatic identification of human faces. A standard view for target images is defined using internal facial features, i.e., the two eyes and the mouth, as steady reference points of the human face. Because reliable detection of such facial features is not an easy task in practice, the proposed scheme is characterized by a combination of two steps: first, all possible regions of facial features are extracted using a color image segmentation algorithm, then the target image is selected from among the candidates defined by tentative combination of the three reference points, through applying the classification framework using the sub-space method. Preliminary experiments on the scheme's flexibility based on subjective assessment indicate a stability of nearly 100% in consistent extraction of target images in the standard view, not only for familiar faces but also for unfamiliar faces, when the input face image roughly matches the front view. By combining this scheme for normalizing images into the standard view with an image matching technique for identification, an experimental system for identifying faces among a limited number of subjects was implemented on a commercial engineering workstation. High success rates achieved in the identification of front view face images obtained under uncontrolled conditions have objectively confirmed the potential of the scheme for accurate extraction of target images.

As RAMs become dense, their reliability reduces because of complex interactions between memory cells and soft errors due to alpha particle radiations. In order to rectify this problem, RAM manufacturers have started incorporating on-chip (built-in) ECC. In order to minimize the area overhead of on-chip ECC, the same technology is used for implementing the check bits and the information bits. Thus the check bits are exposed to the same failure modes as the information bits. Furthermore, faults in the check bits will manifest as uncorrectable multiple errors when a soft error occurs. Therefore it is important to test the check bits for all failure modes expected of other cells. In this paper, we formulate the problem of testing RAMs with on-chip ECC capability. We than derive necessary and sufficient conditions for testing the check bits for arbitrary and adjacent neighborhood pattern sensitive faults. We also provide an efficient solution to test a memory array of N bits (including check bits) for 5-cell neighborhood pattern sensitive faults in O (N) reads and writes, with the check bits also tested for the same fault classes as the information bits.

Since its successful launch in February of 1992, the Japan Earth Resources Satellite-1 (JERS-1) has been sending back high resolution images of the earth for various studies, including the investigation of earth resources, the preservation of environments and the observation of coastal lines. Currently, received images are processed using the Earth Resources Satellite Data Information System (ERSDIS). The ERSDIS is a high speed image processing system utilizing an extended cellular array processor as its main processing module. The extended cellular array processor (CAP), consisting of 4096 processing elements configured into a two-dimensional array, is designed to have many parallel processing optimizing capabilities targetting large-scale image processing at a high speed. This paper desctribes a typical image processing flow, the structure of the ERSDIS, and the details of the CAP design.

This paper discusses methods and numerical simulations of one and two dimensional profilings for an arbitrary convex conducting target using the electromagnetic backscattering. The inversions for profile reconstructions are based upon the modified extended physical optics method (EPO). The modified EPO method assumes the modified physical optics current properly over the entire surface of conducting scatterers. First, the cross sectional area along a line of sight is reconstructed by performing iteratively the Fourier transform of the backscattering field in the frequency domain. Second, the two dimensional profile is reconstructed by synthesizing the above one dimensional results for several incident angles. Numerical simulation results of the target profiling are shown for spheroids and cone-spheroid.

This paper proposes a new method for automatic improvement in image quality through adjusting the image sharpness. This method does not need prior knowledge about image blur. To improve image quality, the sharpness must be adjusted to an optimal value. This paper shows a new method to evaluate sharpness without MTF. It is considered that the human visual system judges image sharpness mainly based upon edge area features. Therefore, attention is paid to the high spatial frequency components in the edge area. The value is defined by the average intensity of the high spatial fequency components in the edge area. This is called the image edge sharpness" value. Using several images, edge sharpness values are compared with experimental results for subjective sharpness. According to the experiments, the calculated edge sharpness values show a good linear relation with subjective sharpness. Subjective image sharpness does not have a monotonic relation with subjective image quality. If the edge sharpness value is in a particular range, the image quality is judged to be good. According to the subjective experiments, an optimal edge sharpness value for image quality was obtained. This paper also shows an algorithm to alter an image into one which has another edge sharpness value. By altering the image, which achieves optimal edge sharpness using this algorithm, image sharpness can be optimally adjusted automatically. This new image improving method was applied to several images obtained by scanning photographs. The experimental results were quite good.

Many simulators in several fields use the finite difference method and they must solve the large sparse linear equations related. Particularly, if we use the direct solution method because of the convergency problem, it is necessary to adopt a method that can reduce the CPU time greatly. The Multi-Step Diakoptics (MSD) method is proposed as a parallel computation method with a direct solution which is based on Diakoptics, that is, a tearing-based parallel computation method for the sparse linear equations. We have applied the MSD algorithm for one, two and three dimensional finite difference methods. We require a parallel schedule that automatically partitions the desired object's region for study, assigns the processor elements to the partitioned regions according to the MSD method, and controls communications among the processor elements. This paper describes a parallel scheduling that was extended from a one dimensional case to a three dimensional case for the MSD method, and the evaluation of the algorithm using a massively parallel computer with distribuled memory(AP1000).

In this paper we present a method to generate test sequences for stuck-at faults in sequential circuits which have distinguishing sequences. Since the circuit may have no distinguishing sequence, we use two design techniques for circuits which have distinguishing sequences. One is at state transition level and the other is at gate level. In our proposed method complete test sequence can be generated. The sequence consists of test vectors for the combinational part of the circuit, distinguishing sequences and transition sequences. The test vectors, which are generated by a combinational test generator, cause faulty staes or faulty output responses for a fault, and disinguishing sequences identify the differences between faulty states and fault free states. Transition sequences are necessary to make the state in the combinational vectors. And the distinguishing sequence and the transition sequence are used in the initializing sequence. Some techniques for shortening the test sequence is also proposed. The basic ideas of the techniques are to use a short initializing sequence and to find the order in concatenating sequences. But fault simulation is conducted so as not to miss any faults. The initializing sequence is obtained by using a distinguishing sequence. The efficiency of our method is shown in the experimental results for benchmark circuits.

A fast and efficient heuristic hierarchical global router for Sea-of-Gates(SOG) with embedded macro-blocks is described. The key point in the method is carry out a new optimal domain decomposition scheduling at every hierarchical level. This scheduling is intended to avoid macro-block-through wirings and to reduce wiring congestion near macro-blocks which may occur at lower levels. The new global router yielded superior results compared with previous hierarchical routers and a non-hierarchical maze router by evaluating with several actual SOG circuits including a 300K gate master chip and benchmark data supplied from MCNC. Overflows were reduced to one-half or one-quarter for macro-block embedded data compared with previous hierarchical routers. Concerning the running time, the router remarkably outperformed the non-hierarchical maze router, which took more than 390 times longer time for the tested large data.

Recently, a flexible image database retrieval system where image keywords can be captured automatically is strongly required, in order to manage a practical number of image data successfully. However, image recognition/understanding technology level is not generally sufficient enough to achieve this requirement. In order to overcome this problem, a new type of image database framework is proposed in this paper. In the proposed system, image keywords are extracted in fully-automated fashion by the flexible and generalized image recognition system. Image keywords employed in this system are a collection of recognized objects in the image, where achieved recognition levels are allowed to be intermediate or imperfect. The concept of recognition thesaurus" has been introduced to manage these various abstraction level of kerwords successfully. As an embodiment of this concept, an experimental image database with various types of sports scenes has been implemented and various retrieval evaluations have been performed. Experimental results reveal the effectiveness of the proposed method.

In the future, it will be necessary that robot technology or environmental technology has an auditory function of recognizing sound expect for speech. In this letter, we propose a recognition system for the species of birds receiving birdcalls, based on network technology. We show the first step of a recognition system for the species of birds, as an application of a recognition system for environmental sound.

High performances of CMOS/SOI inverter by simulations of analytical model, reducing the poly-Si gate thickness (tm), and experiments are verified and proposed. It is shown that the tm and gate oxide thickness(tox) are correlated to gate fringing capacitance, which largely influences on the Propagation Delay Time(TPD). Contributions of gate fringing capacitance to CMOS/SIMOX inverter time delay in deep submicrometer gate devices are propounded. Measurements of the fifty-one stage ring oscillator's TPDs are completed for comparison with analytical model. Simulation results by the analytical model, including Time-Dependent Gate Capacitance (TDGC) model, agree well with the experimental results at the same conditions. Simulation results are also predicted that SOI technology is promising for speed enhancement by reducing the poly-Si gate thickness, while the tox remains constant. It is concluded that the TPDs by reducing the tm to zero are improved up to about two times faster than typically fabricated ring oscillator at 350 nm of the tm in deep-submicrometer gate CMOS/SIMOX inverters at room temperature.

The transient scattering of a half sine pulse wave by a conducting rectangular cylinder with an open sidewall is rigorously analyzed by using the point matching method (taking into account the edge condition exactly) combined with the fast inversion of Laplace transform. Numerical results are presented for back scattered and forward scattered responses of the far fields when a half sine pulse is incident on the open side and the closed side of the cylinder. The physical meaning of the transient responses is discussed in detail. The comparison of the responses with those by a perfect conducting rectangular cylinder is presented.

Radar imaging technique is one of the most powerful tool for underground detection. However, performance of conventional methods is not sufficiently high when the observational direction or the aperture size is restricted. In the present paper, an image reconstruction method based on a model fitting with nonlinear least-squares has been developed, which is applicable to arbitrarily arranged arrays. Reconstruction is executed on the assumption that targets consist of discrete point scatterers embedded in a homogeneous medium. Model fitting is iterated as the number of point target in the assumed model is increased, until the residual in fitting becomes unchanged or small enough. A penalty function is used in nonlinear least-squares to make the algorithm stable. Fundamental characteristics of the method revealed with computer simulation are described. This method focuses a much sharper image than that obtained by the conventional aperture synthesis technique.

For each two positive integers r, s, let [1DCM(r)-Time(ns)] ([1NCM(r)-Time(ns)]) and [1DCM(r)-Space(ns)] ([1NCM(r)-Space(ns)]) be the classes of languages accepted in time ns and in space ns, respectively, by one-way deterministic (nondeterministic) r-counter machines. We show that for each X{D, N}, [1XCM(r)-Time(ns)][1XCM(r+1)-Time(ns)] and [1XCM(r)-Space(ns)][1XCM(r+1)-Space(ns)]. We also investigate the relationships between one-way multicounter machines and cooperating systems of one-way finite automata. In particular, it is shown that one-way (one-) counter machines and cooperating systems of two one-way finite automata are equivalent in accepting power.

String grammars (languages) have been extensively studied from 60's. On the other hand, the transformational grammar, proposed by Chomsky, contains the transformation from the set of derivation trees of context-free language to the surface set. And the grammar regarded a tree as an input sentence to some transducer. After that from latter half of 60's, the studies of acceptor, transducer, and so on, whose input is a tree, have been done extensively. In this paper we propose, as a model, a new type of transducer which translates trees into trees and investigate its fundamental properties. The model proposed here is the pushdown tree transducer (for shortly PDTT) that is an extension of the finite state tree transducer discussed by J. W. Thacher, W. C. Rounds, J. Engelfriet, and so on. The main subjects discussed here (we consider only top-down case (t-PDTT)), are as follows: (1) final state t-PDTT translation is equivalent to empty stack t-PDTT translation and vice versa, (2) for any t-PDTT, a single state t-PDTT which is equivalent to it always exists, (3) as a standard form the symmetric stack form t-PDTT is proposed and based on this, it is shown that any single state t-PDTT can be always converted into a linear stack t-PDTT, and so on.

The antennas for subsurface radar are usually covered with a conducting cavity to prevent the radiation field from affecting the electromagnetic environment and to protect the received field from external noises. Furthermore, radiowave absorber is attached to the interior wall of the cavity in order to suppress the multiple reflections in the cavity. In this paper, the characteristics of the two-dimensional cavity-backed antenna having the absorber and the over-all properties of this subsurface radar due to buried objects are numerically analyzed by the Finite-Difference Time-Domain method. It is shown that the pulse propagation in the ground is confined to the narrow region due to the cavity. It is also shown that the multiple reflections in the cavity are effectively suppressed by choosing the suitable absorber, and so that the distinctive pulse echo can be obtained.

A modern architect can not design high performance computer architecture without thinking all factors of performance from hardware level (logic/layout design) to system level (application programs, operating systems, and compilers). For computer architecture design, there are few practical CAD tools, which support design activities of the architect. In this paper, we propose a CAD tool, called COACH, for computer architecture design. COACH supports architecture design from hardware level to system level. To make a high-performance general purpose computer system, the architect evaluates system performance as well as hardware level performance. To evaluate hardware level performance accurately, logic/layout synthesis tools and simulator are used for evaluation. Logic/layout synthesis tools translate the architecture design into logic circuits and layout pattern and simulator is used to get accurate information on hardware level performance which consists of clock frequency, the number of transistors, power consumption, and so on. To evaluate system level performance, a compiler generator is introducd. The compiler generator generates a compiler of a programming language from the desripition of architecture design. The designed architecture is simulated in the behavior level with programs compiled by the compiler, and the architect can get information on system level performance which consists of program execution steps, etc. From both hardware level performance and system level performance, the architect can evaluate and revise his/her architecture, considering the architecture from hardware level to system level. In this paper, we propose a new design methodology which uses () logic/layout synthesis tools and simulators as tools for architecture design and () a compiler generator for system level evaluation. COACH, a CAD system based on the methodology, is discussed and a prototype of COACH is implemented. Using the design methodology, two processors are designed. The result of the designs shows that the proposed design methodology are effective in architecture design.