This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.

This letter presents a new algorithm for echo cancellers, which prevents the reduction of echo return loss due to a double-talk. The essence of the algorithm is to introduce signal delays to avoid the reduction. A convergence condition in the algorithm was examined by using the IIR filter expression of the NLMS algorithm, and it was concluded that the IIR filter should be a low pass filter with unity gain. The condition is accomplished by selecting a small step gain.

Digital neural networks are suitable for WSI implementation because their noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-µm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.

In this paper, we present an efficient method for the fault simulation of the reconvergent fan-out stem. Our method minimizes the fault propagating region by analyzing the topology of the circuit, whose region is smaller than that of Tulip's. The efficiency of our method is illustrated by experimental results for a set of benchmark circuits.

The test pattern generation for sequential circuits is more difficult than that for combinational circuits due to the presence of memory elements. Therefore we proposed a method for synthesizing sequential circuits with testability in the level of state transition table. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. In this case the checking sequence which do a complete verification of the circuit can be test pattern. The checking sequence have been impractical due to the longer checking sequence required. However, in this paper, we have discussed the condition to reduce the length of checking sequence, then by using suitable state assignment codes sequential circuits with much shorter checking sequences can be realized. A heuristic algorithm of the state assignment which reduce the length of checking sequence is proposed and the algorithm and reduced checking sequence are presented with simple example. The state assignment is very simple with the state matrix which represents the state transition. Furthermore some experimental results of automated synthesis for the MCNC Logic Synthesis Workshop finite state machine benchmark set have shown that the state assignment procedure is efficient for reducing checking sequences.

This paper reviews the potential possibility and present status of trans-polyacetylene research toward realization of soliton molecular devices utilizing characteristics of the quasi-one-dimensional conductor. Properties of solitons in polyacetylene are summarized from a point of view to produce a new microelectronics beyond Si-LSI's. The limiting performance of soliton LSI's are roughly estimated. One bit information is stored in only 420 2. The information transmission rate of a wiring is 2104 Gb/s. The delay time per gate is 0.05 ps. For realization of this high performance devices, a lot of research must be carried out in future. A new circuit with new principles of operations must be developed to achieve the performance, where a localized soliton or a localized group of solitons are treated. Some systems, which may lead to development of logic circuits, are proposed. The problems in crystal quality and fabrication process are also discussed and some means against them are presented.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

The authors examined the effect of feedbacking information on learners of their test results obtained through computerized tests. The learner's acceptability of computerized tests was revealed to be improved by distribution and explanation of newly devised feedback charts including data on one's response history and response latency during computerized testing that was carried out in formative evaluation. The feedback chart composed of graphic representation of relationship between degree of difficulty of each question and its response latency got a particularly high evaluation among learners. It was revealed that types of feedback chart that stood highest in learner's estimate varied with the learner traits. This observation will serve to develop educational systems that incorporate computerized tests into school lessons.

This paper's main objective is to clearly describe the construction of a universal code for minimizing Davisson's minimax redundancy in a range where the true model and stochastic parameters are unknown. Minimax redundancy is defined as the maximum difference between the expected persymbol code length and the per-symbol source entropy in the source range. A universal coding scheme is here formulated in terms of the weight function, i.e., a method is presented for determining a weight function which minimizes the minimax redundancy even when the true model is unknown. It is subsequently shown that the minimax redundancy achieved through the presented coding method is upper-bounded by the minimax redundancy of Rissanen's semi-predictive coding method.

A method to analyze two-pattern test capabilities of autonomous test pattern generator (TPG) circuits for use in built-in self-testing are described. The TPG circuits considered here include arbitrary autonomous linear sequential circuits in which outputs are directly fed out from delay elements. Based on the transition matrix of a circuit, it is shown that the number of distinct transitions in a subspace of state variables can be obtained from rank of the submatrix. The two-pattern test capabilities of LFSRs, cellular automata, and their fast parallel implementation are investigated using the transition coverage as a metric. The relationships with dual circuits and reciprocal circuits are also mentioned.

It is known that the resolution conversion based on orthogonal transform has a problem that is difference of luminance between the converted image and the original. In this paper, the scale factor of the system employing various orthogonal transforms is generally formulated by considering the DC gain, and the condition of alias free for DC component is indicated. If the condition is satisfied, then the scale factor is determined by only the basis functions.

We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.

A new type jacket cutter for optical fibers is designed, and it is confirmed experimentally that its performance is superior to those of the conventional cutters. Using this new cutter which is mainly consisted of a rotatable fiber holder and a pair of blades separated by a distance of 0.3-0.4mm, only the tight jacket is cut and removed while the primary coating and the fiber are kept intact. As the result, the probability of damage to the fiber surface during jacket removal is reduced to about 0% compared to 10% found in the case of a conventional cutter. This result is useful to increase the reliability of optical fibers during assembling efforts.

To speed up a guided-probe diagnosis process, the number of probed lines needs to be reduced. This paper presents two efficient probing line determination methods by which the number of probed lines is either small or minimum. The concept of fault probability is introduced to reflect the fact that not all gates have the same probability to be faulty. Experimental results show the effectiveness of the proposed methods.

This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

An estimation method of region is presented, in which a solution path of the so-called Newton type homotopy equation in guaranteed to exist, it is applied to a certain class of uniquely solvable nonlinear equations. The region can be estimated a posteriori, and its upper bound also can be estimated a priori.

To improve measurement accuracy and speed, a switched-capacitor capacitance measurement circuit with the vernier scale is developed. Its process consists of a coarse measurement by charge-balancing A-D conversion and a fine measurement by single-slope A-D conversion. a prototype using discrete components confirms the principles of operation.

This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N2 to (N/D)2. Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

A wavelength path (WP) network management scheme is proposed for a photonic network. Multimedia data streams are integrated into a single-mode fiber using wave-length division WP multiplexing; both analog/digital and STM/ATM communications are handled. The WP management scheme using WP blocks (WPBs) with guard bands is described. An initially assigned WP does not use the guard band and most bandwidth changes made to accommodate WP changes occur within the original WPB using the guard band. An effective WP assignment method based on a recursive packing scheme is also proposed. The proposed WP packing scheme with guard band realizes a maximum network efficiency of 98%, and the probability of WP reassignment is under 10%. The techniques introduced in this paper permit the realization of flexible and effective multimedia services with a multimedia photonic network.

Since semiconductor memory chip has been growing rapidly in its capacity, memory testing has become a crucial problem in RAMs. This paper proposes a new RAM test algorithm, called generalized marching test (GMT), which detects static and dynamic pattern sensitive faults (PSF) in RAM chips. The memory array with N cells is partitioned into B sets in which every two cells has a cell-distance of at least d. The proposed GMT performs the ordinary marching test in each set and finally detects PSF having cell-distance d. By changing the number of partitions B, the GMT includes the ordinary marching test for B1 and the walking test for BN. This paper demonstrates the practical GMT with B2, capable of detecting PSF, as well as other faults, such as cell stuck-at faults, coupling faults, and decoder faults with a short testing time.