The increasing size and complexity of integrated circuits has lead to the development of advanced algorithms and techniques for circuit simulation. The majority of circuit simulators rely on the Newton-Raphson algorithm for the solution of nonlinear equations that arise from the circuit description. Unfortunately, a good estimate of the root to be found is needed for the algorithm to converge. The convergence rate of the algorithm is quadratic once the method gets "close enough" to the solution, but before reaching this point the method may follow a complex route through unrealistic values of the circuit variables, leading eventually to divergence. Simulations performed with SPICE on several test circuits reveal that during the first iterations of the Newton-Raphson algorithm internal node voltages exceed the power supply voltage of several orders of magnitudes even for simple circuits. A new simulation program called MUSIC (Multilevel Simulator for Integrated Circuits) has been developed to overcome these drawbacks. In MUSIC the circuit to be simulated is decomposed in subcircuits, which may contain instances of other subcircuits up to any nesting level. Subcircuits are then simulated independently with a multilevel Newton algorithm permitting to reduce both the large oscillations that circuit variables undergo during the simulation process and the number of iterations necessary for the circuit to converge. The novel feature of this multilevel algorithm is the propagation of the already calculated terminal voltages, which become known after a subcircuit has converged, to the subcircuits connected to same terminals. In this way the information regarding node voltages is propagated through the network without constraining conditions that do not have physical counterpart. Simulations performed on chains of inverters and a 4-bit full adder evidence how MUSIC is able to improve the convergence rate and to reduce the intermediate voltage spikes.

Among various photonic switching technologies, photonic frequency division multiplexing technology is most promising. In this paper a novel photonic FDM (Frequency Division Multiplexing) system is proposed. The proposed system consists of n (multiplicity of frequencies) independent subnetworks, each of which is identified by a specific frequency, and of which each network topology is identical. When a connection is required by a terminal, the network selects a subnetwork that can afford it, and assigns a frequency representing the selected subnetwork to the terminal. This system eliminates frequency converting devices and traffic concentration equipment, which will reduce the size and cost of the system. A very small sized switching system of very large capacity will be easily realized. In this paper, first we will address the basic concept of the proposed system, and then discuss some technical problems and their solutions concerning network configuration, switch matrix structure, subscriber network configuration, control scheme and frequency multiplicity. Some experimental results are also mentioned.

The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.

A photonic network with a space- and frequency switching capability is proposed. It provides point-to-point and point-to-multipoint connections without internal blocking. The switching network exclusively uses frequency switching stages and a shared-medium architecture. Our proposal is compared with similar published networks which are either also constructed solely from frequency switching stages or from frequency and space switching stages. It is shown that the proposed switching network features fewer optical and opto-electronic components, fewer different types of component/module, lower losses, a higher capacity and an easier expansibility.

We investigated the impact of velocity overshoot effect on collector signal delay of bipolar devices by using Monte Carlo simulation method. We found that insertion of an i-layer (lightly doped, intrinsic layer) between base and collector can increase the delay, but the strength of this effect is a function of the i-layer thickness. When the i-layer becomes thinner, the problem of increasing delay seems to disappear. This recovery of delay is realised with a mechanism which is completely different from that in drift-diffusion model.

This paper describes modeling and simulation of submicron NMOSFET current drive focusing on carrier velocity-saturation effects. A new simple analytical model is proposed which predicts a significant degradation of drain current in sub- and quarter-micron NMOSFET's. Numerical two-dimensional simulations clarify that the degradation is namely caused by high lateral electric field along the channel, which leads to deep velocity-saturation of channel electrons even at the source end. Experimental data of NMOSFET's, with gate oxide thickness (Tox) of 9-20 nm and effective channel lengths (Leff) of 0.35-3.0 µm, show good agreement with the proposed model. It is found that the maximum drain current at the supply voltage of Vdd=3.3 V is predicted to be proportional to Leff0.54 in submicron NMOSFET's, and this is verified with experiments.

The demand for large-capacity photonic switching systems will increase as regular broadband ISDN (B-ISDN) spreads and full-motion video terminals replace telephones. Large-scale and economical optical fiber transmission lines have been built based on time-division (TD) multiplexing. To reduce costs, it is important to increase the channel multiplexity of both transmission and switching systems by using TD and wavelength-division (WD) or frequency-division (FD) technologies. We surveyed photonic switching systems' architecture and switching network structures. Switching can be divided into circuit or synchronous transfer mode (STM) switching, and asynchronous transfer mode (ATM) switching. A variety of photonic STM and ATM switching systems based on the two switching technologies have recently been proposed and demonstrated.

Material representations and algorithms are presented for simulation of nanometer lithography. Organic polymer resists are modeled as collections of overlapping spheres, with each sphere representing a polymer chain. Exposure and post-exposure bake steps are modeled at the nanometer scale for both positive and negative resists. The development algorithm is based on the Poisson removal probability for each sphere in contact with developer. The Poisson removal rate for a given sphere is derived from a mass balance relationship with a macroscopic development rate model. Simulations of electron beam lithography with (poly) methyl methacrylate and Shipley SAL-601 reveal edge roughness standard deviations from 2 to 3 nm, leading to linewidth peak-to-peak 3σ variation of 15 to 22 nm. Typical simulations require about 2 MBytes and under 5 minutes on a Sun Sparc 10/41 engineering workstation.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

This paper describes a DBF (Digital Beamforming) technique as a spatial filtering in the radar systems. DBF for a beamformer and an adaptive processor are discussed. An architecture for the beamformer is proposed. The beamformer discussed consists of systolic arrays that can form beams arbitrarily. Antenna radiation patterns measured in an open site are shown. For the adaptive processor, Gram-Schmidt transformation method is attained by using systolic arrays. Proposed is a means to prevent target signals from being suppressed in cells of the systolic arrays and to achieve the convergent characteristics independent of the magnitude of undesired signal power. In order to demonstrate the performance of the proposed processor, a test model of the adaptive processor was developed and tested in multiple undesired signal environment. Test results are indicated.

OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.

This paper newly estimates the yield suppression for 1.5 V-1 Gbit DRAM caused by threshold voltage variation of MOSFET due to microscopic fluctuations in dopant distributions within the channel region and points out the limitation of the conventional redundancy techniques. The yield suppression is estimated for four main circuit blocks, the memory cell transfer transistor, bit line sense amplifier S/A, I/O line differential amplifier D/A, and the peripheral circuit. It is newly found that for 1.5 V-1 Gbit DRAM due to the effect of the newly estimated threshold voltage variation of MOSFET the bit failures of memory cells become the most dominant failure mode and the failure of D/A which can be ignored for 64 Mbit DRAM level can no longer be neglected. Furthermore, the novel optimized redundancy technique for replacing these failure is described.

A new method for simulation of etching and deposition processes has been developed. This method is based on fundamental morphological operations derived from image and signal processing. As the material surface during simulation moves in time, the geometry either increases or decreases. If the simulation geometry is considered as a two-valued image (material or vacuum), etching and deposition processes can be simulated by means of the erosion and dilation operation. Together with a cellular material representation this method allows an accurate and stable simulation of three-dimensional arbitrary structures. Simulation results for several etching and deposition problems demonstrate accuracy and generality of our method.

Pure bend loss of a fiber with a trench section is calculated by the alternating-direction implicit finite-difference method. The dependence of the loss on the trench location is evaluated. The mechanism of the oscillatory behavior of the loss is discussed in terms of a modal approach in a dielectric slab waveguide.

Numerical simulation of the hydrodynamic semiconductor device equations requires powerful numerical schemes. A Space-time Galerkin/Least-Squares finite element formulation, that has been successfully applied to problems of fluid dynamic, is proposed for the solution of the hydrodynamic device equations. Similarity between the equations of fluid dynamic and semiconductor devices is discussed. The robustness and accuracy of the numerical scheme are demonstrated with the example of a single electron carrier submicron silicon MESFET device.

As a general basis for constructing a cooperative and flexible dialogue system, we are interested in modelling the inference process of an agent who participates in a dialogue. For this purpose, it is natural and powerful to model it in his general cognitive framework for problem solving. This paper presents such a framework. In this framework, we represent agent's mental states in the form called Mental World Structure, which consists of multiple mental worlds. Each mental world is a set of mental propositions and corresponds to one modal context, that is, a specific point of view. Modalities in an agent's mental states are represented by path expressions, which are first class citizens of the system and can be composed each other to make up composite modalities. With Mental World Structure, we can handle modalities more flexibly than ordinary modal logics, situation theory and other representation systems. We incorporate smoothly into the structure three basic inference procedures, that is, deduction, abduction and truth maintenance. Precise definitions of the structure and the inference procedures are given. Furthermore, we explain as examples, several cooperative dialogues in our framework.

Central switches are expected to operate at the rate of Terabit per second in high speed networks, like the B-ISDN. Photonic switches using lightwave technology based on wavelength division multiplexing (WDM) and frequency division multiplexing (FDM) are promising ones for high speed switching. Such lightwave networks are mainly divided into two groups, according to the number of hops required for packets to arrive at their destinations: single-hop networks such as networks using star coupler and multihop networks such as Manhattan Street Network and ShuffleNet. In this paper we focus our attention on multihop networks and propose a mesh network, referred to as RookNet, for high speed communication. The average transmission delay time and maximum throughput of RookNet is approximately analyzed. It is shown that, as the number of nodes goes to infinity, the maximum throughput aproaches 0.433 and 0.485 when each node is equipped with no internal buffer and internal buffers of infinite capacity for relayed packets, respectively.

The connection admission control is one of preventive traffic control in ATM networks. The one objective of connection admission control is to keep the network load moderate so as to achieve a performance objective associated with quality of services (QOS). Because the cell loss rate is more sensitive to offered load than the average queuing delay in ATM networks, QOS requirement associated with cell loss rate is considered. The connection admission control acts as one of the major roles in traffic control. The job of connection admission control is to make an acceptance decision for connection set-up request to control the network load. This paper proposed and evaluated a connection admission control method. The proposed method is suitable for real time operation even in large diversity of connection types, because the amount of calculation for connection admission control is reduced remarkably compared to conventional algorithms. Moreover, the amount of calculation for the algorithm does not increase even when the number of connection types increases. The proposed method uses probability function for the number of cells transferred from multiplexed connections and uses recursive equations in estimating cell loss rate.

Checkpointing is one of the most powerful tools to operate a computer system with high reliability. We should execute the optimal checkpointing in some sense. This note shows the optimal checkpoint sequence minimizing the expected loss, Numerical examples are shown for illustration.