A new approach to the problem of optimal software testing time is described. Most models implicitly assume the testing is terminated at the end of a prescribed period of time without user's approval. It means the release time and the in-service reliability are determined unilaterally by the developer. If software developer uses and maintains it, the assumption is appropriate. But, it may be inappropriate, if a software requiring more stringent reliability is developed by second party on a contract basis. In this case, the time of release is usually determined with the user's approval. To overcome the weaknesses of the assumption, a two stage testing with failure-free release policy is proposed. A software, after being tested by the developer for some time (in-house testing), is transferred to acceptance testing performed jointly with the user. During the acceptance testing, it is released when τ units of time specified by user is observed to be failure-free for the first time. The policy may be attractive to a user because he can determine the time of release, and extend the testing time by increasing τ. A software cost model for the policy is developed. For the software developer, an optimal in-house testing time minimizing software cost, and various quantities of interests, such as expected periods of acceptance testing, are derived based on the Jelinski-Moranda software reliability model. Finally, numerical examples are shown to illustrate the results.

A modified illumination technique recently developed is known to improve the resolution and DOF (depth of focus) dramatically. But, it requires substantial modification in optical projection system and has some problems such as low throughput caused by low intensity and poor uniformity. And it is very difficult to adjust illumination source according to pattern changes. To solve these problems, we developed a new illumination technique, named ATOM (Advanced Tilted illumination On Mask) which applies the same concept as quadrupole illumination technique but gives many advantages over conventional techniques. This newly inserted mask gives drastic improvements in many areas such as DOF, resolution, low illumination intensity loss, and uniformity. In our experiments, we obtained best resolution of 0.28µm and 2.0µm DOF for 0.36µm feature sizes with i-line stepper, which is two times as wide as that of conventional illumination technique. We also obtained 0.22µm resolution and 2.0µm DOF for 0.28µm with 0.45NA KrF excimer laser stepper. For complex device patterns, more than 1.5 times wider DOF could be obtained compared to conventional illumination technique. From these results, we can conclude that 2nd generation of 64M DRAM with 0.3µm design rule can be printed with this technology combined with high NA (0.5) i-line steppers. With KrF excimer laser stepper, 256M DRAM can be printed with wide DOF.

An electron beam cell projection system has been developed that can effectively expose the fine, demagnified resultant pattern of repeated and non-repeated patterns such as the 256 Mb DRAM on a semiconductor wafer. Particular attention was given to the beam shaping and deflecting optics, which has two stage deflectors for the cell projection beam selection as well as the beam sizing, and three stage deflectors for objective deflection. The cell mask with a rectangular aperture and multiple figure apertures is fabricated by modified Si wafer processes. A new exposure control data for the cell projection is proposed. This data is fitted for the combination of pattern data for the cell mask projection and pattern data for the variable rectangular shape beam within the divided units of the objective deflection. On this exposure system, selective exposure of the desired pattern becomes possible on the semiconductor wafer while a mounting stage of the wafer is being moved, even if the pattern exposure of the repeated and non-repeated patterns is to be carried out. The total overhead time for selecting a subset of multiple figures and a rectangular aperture of the cell mask is less than 5 seconds/wafer. The estimated throughput of this system is approximately 20 wafers/hour.

A new phase shift lithography method has been developed that allows different integrated circuit features to be focused on different optical planes that conform to the wafer surface topography. In principle, each pattern in the circuit has its own unique focal plane. The direction and magnitude of each focus shift is determined by the design of the shifter patterns. This method is applicable for use with conventional opaque mask patterns and unattenuated phase shift patterns. The characteristics of this multiple-focus-plane technique have been evaluated experimentally and confirmed theoretically through mathematical modeling using TCC optical imaging theory. Experiments were conducted using i-line positive resist processes for different phase-shift patterns. This paper discusses the effects of changes in phase shift and recommends practical mask design approaches.

This paper describes the formation of ultra-thin tantalum oxide capacitors, using rapid thermal nitridation (RTN) of the storage-node polycrystalline-silicon surface prior to low-pressure chemical vapor deposition of tantalum oxide, using penta-ethoxy-tantalum [(Ta(OC2H5)5) and oxygen gas mixture. The films are annealed at 600-900 in dry O2 atmosphere. Densification of the as-deposited film by annealing in dry O2 is indispensable to the formation of highly reliable ultra-thin tantalum oxide capacitors. The RTN treatment reduces the SiO2 equivalent thickness and leakage current of the tantalum oxide film, and improves the time dependent dielectric breakdown characteristics of the film.

The main problem in statistical pattern recognition is to design a classifier. Many researchers point out that a finite number of training samples causes the practical difficulties and constraints in designing a classifier. However, very little is known about the performance of a classifier in small training sample size situations. In this paper, we compare the classification performance of the well-known classifiers (k-NN, Parzen, Fisher's linear, Quadratic, Modified quadratic, Euclidean distance classifiers) when the number of training samples is small.

Recently, efficient algorithms that exploit the separability of nonlinear mappings have been proposed for finding all solutions of piecewise-linear resistive circuits. In this letter, it is shown that these algorithms can be extended to circuits containing piecewise-linear resistors that are neither voltage nor current controlled. Using the parametric representation for these resistors, the circuits can be described by systems of nonlinear equations with separable mappings. This separability is effectively exploited in finding all solutions. A numerical example is given, and it is demonstrated that all solutions are computed very rapidly by the new algorithm.

The Minimum Covering Run (MCR) expression used for representing binary images has been proposed [1]-[3]. The MCR expression is an adaptation from horizontal and vertical run expression. In the expression, some horizontal and vertical runs are used together for representing binary images in which total number of them is minimized. It was shown that, sets of horizontal and vertical runs representing any binary image could be viewed as partite sets of a bipartite graph, then the MCR expression of binary images was found analogously by constructing a maximum matching as well as a minimum covering in the corresponding graph. In the original algorithm, the most efficient algorithm, proposed by Hopcroft, solving the graph-theoretical problems mentioned above, associated with the Rectangular Segment Analysis (RSA) was used for finding the MCR expression. However, the original algorithm still suffers from a long processing time. In this paper, we propose two new efficient MCR algorithms that are beneficial to a practical implementation. The new algorithms are composed of two main procedures; i.e., Partial Segment Analysis (PSA) and construction of a maximum matching. It is shown in this paper that the first procedure which is directly an improvement to the RSA, appoints well a lot of representative runs of the MCR expression in regions of text and line drawing. Due to the PSA, the new algorithms reduce the number of runs used in the technique of solving the matching problem in corresponding graphs so that satisfactory processing time can be obtained. To clarify the validity of new algorithms proposed in this paper, the experimental results show the comparative performance of the original and new algorithms in terms of processing time.

This paper studies the problem of embedding a graph into a book with nodes on a line along the spine of the book and edges on the pages in such a way that no edge crosses another. Atneosen as well as Bernhart and Kainen has shown that every graph can be embedded into a 3-page book when each edge can be embedded in more than one page. The time complexity of Bernhart and Kainen's method is Ω(ν(G)), where ν(G) is the crossing number of a graph G. A new 0(mn) algorithm is derived in this paper for embedding a graph G=(V, E), where m=│E│ and n= │V│ . The number of points at which edges cross over the spine in embedding a complete graph into a 3-page book is also investigated.

This paper proposes new algorithms for adaptive FIR filters. The proposed algorithms provide both fast convergence and small final misadjustment with an adaptive step size even under an interference to the error. The basic algorithm pays special attention to the interference which contaminates the error. To enhance robustness to the interference, it imposes a special limit on the increment/decrement of the step-size. The limit itself is also varied according to the step-size. The basic algorithm is extended for application to nonstationary signals. Simulation results with white signals show that the final misadjustment is reduced by up to 22 dB under severe observation noise at a negligible expense of the convergence speed. An echo canceler simulation with a real speech signal exhibits its potential for a nonstationary signal.

In a distributed-memory parallel-processing system, the overhead of data transfer among the processors is so large that it is important to reduce the data transfer. We consider the data transfer in evaluating an expression consisting of data distributed among the processors. We propose some algorithms which assign the operators in the expression to the processors so as to minimize the number or the cost of data transfers, on the condition that the data allocation to the processors is given. The basic algorithm is given at first, followed by some variations.

This paper proposes the Total High Performance Time as a performance-related reliability measure in degradable/recoverable real-time systems. This measure reflects the effect of system behavior in pending states that are temporary states between the normal state and degraded states where the system operates in a degraded mode as a consequence of component failures. Such systems have to perform not only normal procedures but also error/recovery procedures in pending states, so the performance there is lower than that in the degraded states. In real-time systems, if performance is less than a lower limit, the response time for on-line transactions cannot meet the deadline. The consequences of failing to meet the deadline could be system failure. Therefore, the system reliability is affected significantly by whether the performance there is higher than the lower limit or not. A state where the level of performance is higher than the lower limit is called a High Performance State. We define the Total High Performance Time as the total time that the system spends operating in High Performance States. Moreover, this paper explains how to utilize the Total High Performance Time in system design. We model a method of controlling a system in pending states by using Extended Stochastic Petri Nets and obtain the characteristics necessary for evaluating the Total High Performance Time by analyzing the model. This approach is applied to a storage system that controls mirrored disks, and shown to be helpful for designing a method of controlling a system in pending states, which has been considered difficult because of the trade-off between performance and reliability.

New critical-dimension controlling technique of off-axis illumination for aperiodic patterns has been developed. By means of arranging not-imaging additional pattern near 0.25 micron isolated patterns, the depth of focus of an isolated pattern was improved as well as the periodic patterns. Simulation and experimental results were verified on a 0.48 numerical-aperture, KrF excimer laser stepper. Using new deep-ultra-violet hardening technique for chemically amplified positive resist, the critical dimension loss of resist pattern was prevented. 0.25 micron design rule pattern was obtained with excellent mask linearity without critical-dimension-loss. The combination techniques are achieved quarter micron design rule complex circuit pattern layouts.

The scope of this paper is the realization of FIR digital filters with an emphasis on linear phase and maximally flat cases. The transfer functions of FIR digital filters are polynomials and polynomial evaluation algorithms can be utilized as realization schemes of these filters. In this paper we investigate the application of a class of polynomial evaluation algorithms called "recursive triangles" to the realization of FIR digital filters. The realization of an arbitrary transfer function using De Casteljau algorithm, a member of the recursive triangles used for evaluating Bernstein polynomials, is studied and it is shown that in some special and important cases it yields efficient modular structures. Realization of two dimensional filters based on Bernstein approximation is also considered. We also introduce recursive triangles for evaluating the power basis representation of polynomials and give a new multiplier-less maximally flat structure based on them. Finally, we generalize the structure further and show that Chebyshev polynomials can also be evaluated by the triangles. This is the triangular counterpart of the well-known Chebyshev structure. In general,the triangular structures yield highly modular digital filters that can be mapped to an array of concurrent processors resulting in high speed and effcient filtering specially for maximally flat transfer functions.

Central switches are expected to operate at the rate of Terabit per second in high speed networks, like the B-ISDN. Photonic switches using lightwave technology based on wavelength division multiplexing (WDM) and frequency division multiplexing (FDM) are promising ones for high speed switching. Such lightwave networks are mainly divided into two groups, according to the number of hops required for packets to arrive at their destinations: single-hop networks such as networks using star coupler and multihop networks such as Manhattan Street Network and ShuffleNet. In this paper we focus our attention on multihop networks and propose a mesh network, referred to as RookNet, for high speed communication. The average transmission delay time and maximum throughput of RookNet is approximately analyzed. It is shown that, as the number of nodes goes to infinity, the maximum throughput aproaches 0.433 and 0.485 when each node is equipped with no internal buffer and internal buffers of infinite capacity for relayed packets, respectively.

Photonic ATM switching systems with Terabit/s throughput are desirable for future broadband ISDN systems. Since electronic LSI-based ATM switching systems are planned to have the throughput of 160Gb/s, a photonic ATM switching system should take the role of the highest layer in a hybrid switching network which includes electronic LSI-based ATM switching systems as its sub-system. This report discusses the state-of-the-art photonic devices needed for a frequency-self-routing ATM photonic switching system with maximum throughput of 5Tb/s. This kind of systems seems to be a moderate system for the first phase photonic switching system with no insuperable obstacle for initiating development, even though none of the devices and technologies required have yet been developed to meet the specifications. On the contrary, for realizing further enlarged throughput as the second-phase photonic switching system, there are huge fundamental research projects still remaining for establishing the technology utilizing the spectrum broadened over 120nm and highly-dense FDM technologies based on homodyne coherent detection, if supposing a simple architecture. "Ultra devices" seem to be the photonic devices based on new tailored materials of which gain and refractive index are designed to realize ultra-wide spectrum utilization.

A new method for simulation of etching and deposition processes has been developed. This method is based on fundamental morphological operations derived from image and signal processing. As the material surface during simulation moves in time, the geometry either increases or decreases. If the simulation geometry is considered as a two-valued image (material or vacuum), etching and deposition processes can be simulated by means of the erosion and dilation operation. Together with a cellular material representation this method allows an accurate and stable simulation of three-dimensional arbitrary structures. Simulation results for several etching and deposition problems demonstrate accuracy and generality of our method.

A two-dimensional self-aligned silicide (SALICIDE) model has been developed using the general-purpose process simulator OPUS. A new two-dimensional growth model is proposed. Utilizing a newly-difined effective silicide thickness, the model accounts both silicon-diffusion and metal-diffusion limited silicide growth. Silicide lateral-growth along a sidewall spacer is successfully simulated for Si-diffusion limited silicide growth. Complete MOSFET process simulation with a SALICIDE process is demonstrated for the first time.

This paper briefly reviews recent studies on free-space photonic switches, and discusses classifications, applications and technical issues to be solved. The free-space photonic switch is a switch that uses light beam interconnections based on free-space optics instead of guided-wave optics. A feature of the free-space switch is its high-density three-dimensional structure that enables compact large-scale switches to be created. In this paper, the free-space switches are classified by their various attributes such as logical network configuration, path-establishment method, number of physical stages, signal-waveform transmission form, interconnection optics and so on. The logical network configuration (topological geometry or topology) is strongly related to the advantages of the free-space switches over the guided-wave switches. The path-establishment method (path-shifting/branching-and-gating) and the number of physical stages (single-stage/multistage) are related to physical switching characteristics. Signal-waveform transmission form (analog/digital) is related to switch application. Interconnection optics (imaging system/micro-beam system) is related to the density and volume of the switching fabric. Examples of the free-space switches (single-stage, analog multistage, digital multistage and photonic ATM switches) are described. Possible applications for analog switches are subscriber-line concentrators, inter-module connectors, and switching networks for parallel or distributed computer systems. Those for digital switches include multistage space-division switches in time-division circuit-switching or packet switching systems (including asynchronous transfer mode [ATM] switching system) for both communications switching systems and parallel/distributed computer systems. Technical issues of the free-space switches (system, device, assembly technique) must be solved before creating practical systems. In particular, the assembly technique is a key issue of the free-space switches.

The demand for large-capacity photonic switching systems will increase as regular broadband ISDN (B-ISDN) spreads and full-motion video terminals replace telephones. Large-scale and economical optical fiber transmission lines have been built based on time-division (TD) multiplexing. To reduce costs, it is important to increase the channel multiplexity of both transmission and switching systems by using TD and wavelength-division (WD) or frequency-division (FD) technologies. We surveyed photonic switching systems' architecture and switching network structures. Switching can be divided into circuit or synchronous transfer mode (STM) switching, and asynchronous transfer mode (ATM) switching. A variety of photonic STM and ATM switching systems based on the two switching technologies have recently been proposed and demonstrated.