This paper proposes a graph-theory-based Euler number computing algorithm. According to the graph theory and the analysis of a mask's configuration, the Euler number of a binary image in our algorithm is calculated by counting four patterns of the mask. Unlike most conventional Euler number computing algorithms, we do not need to do any processing of the background pixels. Experimental results demonstrated that our algorithm is much more efficient than conventional Euler number computing algorithms.

This paper proposes a multiple-fault injection attack based on adaptive control of fault injection timing in embedded microcontrollers. The proposed method can be conducted under the black-box condition that the detailed cryptographic software running on the target device is not known to attackers. In addition, the proposed method is non-invasive, without the depackaging required in previous works, since such adaptive fault injection is performed by precisely generating a clock glitch. We first describe the proposed method which injects two kinds of faults to obtain a faulty output available for differential fault analysis while avoiding a conditional branch in a typical recalculation-based countermeasure. We then show that the faulty output can be obtained by the proposed method without using information from the detailed instruction sequence. In particular, the validity of the proposed method is demonstrated through experiments on Advanced Encryption Standard (AES) software with a recalculation-based countermeasure on 8-bit and 32-bit microcontrollers. We also present a countermeasure resistant to the proposed method.

A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was realized in 0.13,$mu$m CMOS technology. It consists of an analog PLL, a harmonic-rejection mixer and injection-locked frequency doublers to cover the whole 6--18,GHz frequency range. To achieve a low phase noise performance, a sub-sampling PLL with non-dividers was employed. The synthesizer can achieve phase noise $-$113.7,dBc/Hz@100,kHz in the best case and the reference spur is below $-$60,dBc. The core of the synthesizer consumes about 110,mA*1.2,V.

We consider a location-aware store-carry-forward routing scheme based on node density estimation (LA Routing in short), which adopts different message forwarding strategies depending on node density at contact locations where two nodes encounter. To do so, each node estimates a node density distribution based on information about contact locations. In this paper, we clarify how the estimation accuracy affects the performance of LA Routing. We also examine the performance of LA Routing when it applies to networks with homogeneous node density. Through simulation experiments, we show that LA Routing is fairly robust against the accuracy of node density estimation and its performance is comparable with Probabilistic Routing even in the case that that node density is homogeneous.

For a large-sized touch screen, we designed and evaluated a real-time touch microarchitecture using a field-programmable gate array (FPGA). A high-speed hardware accelerator based on a parallel touch algorithm is suggested and implemented in this letter. The touch controller also has a timing control unit and an analog digital convert (ADC) control unit for analog touch sensing circuits. Measurement results of processing time showed that the touch controller with its proposed microarchitecture is five times faster than the 32-bit reduced instruction set computer (RISC) processor without the touch accelerator.

The mobile cloud computing (MCC) paradigm is aimed at integrating mobile devices with cloud computing. In the client-server architecture of MCC, mobile devices offload tasks to the cloud to utilize the computation and storage resources of data centers. However, due to the rapid increase in the traffic demand and complexity of mobile applications, service providers have to continuously upgrade their infrastructures at great expense. At the same time, modern mobile devices have greater resources (communication, computation, and sensing), and these resources are not always fully utilized by device users. Therefore, mobile devices, from time to time, encounter other devices that could provide resources to them. Because the amount of such resources has increased with the number of mobile devices, researchers have begun to consider making use of these resources, located at the “edge” of mobile networks, to increase the scalability of future information networks. This has led to a cooperation based architecture of MCC. This paper reports the concept and design of an resource sharing mechanism that utilize resources in mobile devices through opportunistic contacts between them. Theoretical models and formal definitions of problems are presented. The efficiency of the proposed mechanism is validated through formal proofs and extensive simulation.

As the virtualization technology becomes the core ingredient for recent promising IT infrastructures such as utility computing and cloud computing, accurate analysis of the internal behaviors of virtual machines becomes more and more important. In this paper, we first propose a novel I/O fairness analysis tool for virtualization systems. It supports the following three features: fine-grained, multimodal and multidimensional. Then, using the tool, we observe various I/O behaviors in our experimental XEN-based virtualization system. Our observations disclose that 1) I/O fairness among virtual machines is broken frequently even though each virtual machine requests the same amount of I/Os, 2) the unfairness is caused by an intricate combination of factors including I/O scheduling, CPU scheduling and interactions between the I/O control domain and virtual machines, and 3) some mechanisms, especially the CFQ (Completely Fair Queuing) I/O scheduler that supports fairness reasonable well in a non-virtualization system, do not work well in a virtualization system due to the virtualization-unawareness. These observations drive us to design a new virtualization-aware I/O scheduler for enhancing I/O fairness. It gives scheduling opportunities to asynchronous I/Os in a controlled manner so that it can avoid the unfairness caused by the priority inversion between the low-priority asynchronous I/Os and high-priority synchronous I/Os. Real implementation based experimental results have shown that our proposal can enhance I/O fairness reducing the standard deviation of the finishing time among virtual machines from 4.5 to 1.2.

This paper proposes a name-based routing mechanism called Routing Guidance Name (RGN) that offers new routing management functionalities within the basic characteristics of CCN. The proposed mechanism names each CCN router. Each router becomes a Data Provider for its name. When a CCN Interest specifies a router's name, it is forwarded to the target router according to the standard mechanism of CCN. Upon receiving an Interest, each router reacts to it according to RGN. This paper introduces a new type of node called a Scheduler which calculates the best routes based on link state information collected from routers. The scheduler performs its functions based on RGN. This paper discusses how the proposed system builds CCN FIB (Forwarding Information Base) in routers. The results of experiments reveal that RGN is more efficient than the standard CCN scheme. It is also shown that the proposal provides mobility support with short delay time. We explain a practical mobile scenario to illustrate the advantages of the proposal.

This paper reports a 65nm 8Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation-tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSs as loads, which maximizes the readout margin at any process corner. The STT-MRAM achieves a cycle time of 1.9µs (=0.526MHz) at 0.38V. The operating power is 1.70µW at this voltage. The minimum energy per access is 1.12 pJ/bit when the supply voltage is 0.44V. The proposed STT-MRAM operates at a lower energy than an SRAM when the utilization of the memory bandwidth is 14% or less.

This paper presents a framework for reducing the energy consumption of embedded real-time systems. We implemented the presented framework as both an optimization toolchain and an energy-aware real-time operating system. The framework consists of the integration of multiple techniques to optimize the energy consumption. The main idea behind our approach is to utilize trade-offs between the energy consumption and the performance of different processor configurations during task checkpoints, and to maintain memory allocation during task context switches. In our framework, a target application is statically analyzed at both intra-task and inter-task levels. Based on these analyzed results, runtime optimization is performed in response to the behavior of the application. A case study shows that our toolchain and real-time operating systems have achieved energy reduction while satisfying the real-time performance. The toolchain has also been successfully applied to a practical application.

Boneh et al. proposed the new idea of pairing-based cryptography by using the composite order group instead of prime order group. Recently, many cryptographic schemes using pairings of composite order group were proposed. Miller's algorithm is used to compute pairings, and the time of computing the pairings depends on the cost of calculating the Miller loop. As a method of speeding up calculations of the pairings of prime order, the number of iterations of the Miller loop can be reduced by choosing a prime order of low Hamming weight. However, it is difficult to choose a particular composite order that can speed up the pairings of composite order. Kobayashi et al. proposed an efficient algorithm for computing Miller's algorithm by using a window method, called Window Miller's algorithm. We can compute scalar multiplication of points on elliptic curves by using a window hybrid binary-ternary form (w-HBTF). In this paper, we propose a Miller's algorithm that uses w-HBTF to compute Tate pairing efficiently. This algorithm needs a precomputation both of the points on an elliptic curve and rational functions. The proposed algorithm was implemented in Java on a PC and compared with Window Miller's Algorithm in terms of the time and memory needed to make their precomputed tables. We used the supersingular elliptic curve y2=x3+x with embedding degree 2 and a composite order of size of 2048-bit. We denote w as window width. The proposed algorithm with w=6=2·3 was about 12.9% faster than Window Miller's Algorithm with w=2 although the memory size of these algorithms is the same. Moreover, the proposed algorithm with w=162=2·34 was about 12.2% faster than Window Miller's algorithm with w=7.

Binaural reproduction is one of the promising approaches to present a highly realistic virtual auditory space to a listener. Generally, binaural signals are reproduced using a set of headphones that leads to a simple implementation of such a system. In contrast, binaural signals can be presented to a listener using a technique called “transaural reproduction” which employs a few loudspeakers with crosstalk cancellation for compensating acoustic transmissions from the loudspeakers to both ears of the listener. The major advantage of transaural reproduction is that a listener is able to experience binaural reproduction without wearing any device. This leads to a more natural listening environment. However, in transaural reproduction, the listener is required to be still within a very narrow sweet spot because the crosstalk canceller is very sensitive to the listener's head position and orientation. To solve this problem, dynamic transaural systems have been developed by utilizing contact type head tracking. This paper introduces the development of a dynamic transaural system with non-contact head tracking which releases the listener from any attachment, thereby preserving the advantage of transaural reproduction. Experimental results revealed that sound images presented in the horizontal and median planes were localized more accurately when the system tracked the listener's head rotation than when the listeners did not rotate their heads or when the system did not track the listener's head rotation. These results demonstrate that the system works effectively and correctly with the listener's head rotation.

Researchers have developed several social-based routing protocols for delay tolerant networks (DTNs) over the past few years. Two main routing metrics to support social-based routing in DTNs are centrality and similarity metrics. These two metrics help packets decide how to travel through the network to achieve short delay or low drop rate. This study presents a new routing scheme called Community-Relevance based Opportunistic routing (CROP). CROP uses a different message forwarding approach in DTNs by combining community structure with a new centrality metric called community relevance. One fundamental change in this approach is that community relevance values do not represent the importance of communities themselves. Instead, they are computed for each community-community relationship individually, which means that the level of importance of one community depends on the packet's destination community. The study also compares CROP with other routing algorithms such as BubbleRap and SimBet. Simulation results show that CROP achieves an average delivery ratio improvement of at least 30% and can distribute packets more fairly within the network.

Digital map systems can be categorized, based on the support they provide, into map navigation systems and map touring systems. Map navigation systems put more focus on helping travelers finding routes or directions instantly. By contrast, map touring systems such as Google Maps running on desktop computers are built to support users in developing their routes and survey knowledge before they go for travel. In this paper, traveler conceptual models are proposed as an interaction paradigm to enhance user immersion and interaction experience on map touring systems. A map touring system, MapXplorer, is also introduced as a proof of concept with its system design and implementation explained in detail. Twenty participants were invited to join the user study that investigates users' performance and preferences on navigation and exploration tasks. The results of experiments show that the proposed system surpasses traditional map touring systems on both navigation and exploration tasks for about 50 percent on average, and provides better user experience.

With the development of personal electronic equipment, the use of a smartphone with a tri-axial accelerometer to detect human physical activity is becoming popular. In this paper, we propose a new feature based on FFT for activity recognition from tri-axial acceleration signals. To improve the classification performance, two fusion methods, minimal distance optimization (MDO) and variance contribution ranking (VCR), are proposed. The new proposed feature achieves a recognition rate of 92.41%, which outperforms six traditional time- or frequency-domain features. Furthermore, the proposed fusion methods effectively improve the recognition rates. In particular, the average accuracy based on class fusion VCR (CFVCR) is 97.01%, which results in an improvement in accuracy of 4.14% compared with the results without any fusion. Experiments confirm the effectiveness of the new proposed feature and fusion methods.

For next generation planar lightwave circuit (PLC) devices, high function and high-density integration are required as well as downsizing and cost reduction. To realize these needs, high refractive index difference between a core and a clad $(Delta)$ is required. To use PLC for practical applications, silica-based PLC is one of the most attractive candidate. However, degradation of the optical properties and productivity occur when $Delta$ of the core becomes high. Thus, $Delta$ of most of the conventional PLC with GeO$_2$-SiO$_2$ core is designed less than 2.5%. In this paper, we report a silica-based ultra-high $Delta $ PLC with ZrO$_2$-SiO$_2$ core. 5.5%-$Delta$ ZrO$_2$-SiO$_2$ PLC has been realized with low propagation loss and basic characteristics has been confirmed. Potential of chip size reduction of the ZrO$_2$-SiO$_2$ PLC is shown.

Integrated InP polarization converters based on half-ridge structure are studied numerically. We demonstrate that the fabrication tolerance of the half-ridge structure can be extended significantly by introducing a slope at the ridge side and optimizing the thickness of the residual InGaAsP layer. High polarization conversion over 90% is achieved with the broad range of the waveguide width from 705 to 915~nm, corresponding to a factor-of-two or larger improvement in the fabrication tolerance compared with that of the conventional polarization converters. Finally we present a simple fabrication procedure of this newly proposed structure, where the thickness of the residual InGaAsP layer is controlled precisely by using a thin etch-stop layer.

In this paper, we present a differential dual-modulus prescaler based on an injection-locked frequency divider (ILFD) for satellite low-noise block (LNB) down-converters. We fabricated three-stage differential latches using an ILFD and a cascaded differential divider in a 130-nm CMOS process. The prototype chip core area occupies 40µm × 20µm. The proposed prescaler achieved the locking range of 2.1-10GHz with both divide-by-10 and divide-by-11 operations at a supply voltage of 1.4V. Normalized energy consumptions are 0.4pJ (=mW/GHz) at a 1.4-V supply voltage and 0.24pJ at a 1.2-V supply voltage. To evaluate the tolerance of phase-difference deviation of the input differential pair from the perfect differential phase-difference, 180 degrees, we measured the operational frequencies for various phase-difference inputs. The proposed prescaler achieved the operational frequency range of 2.1-10GHz with an input phase-difference deviation of less than 90 degrees. However, the range of operational frequency decreases as the phase-difference deviation increases beyond 90 degrees and reaches 3.9-7.9GHz for the phase-difference deviation of 180 degrees (i.e. no phase difference). In addition, to confirm the fully locking operation, we measured the spurious noise and the phase noise degradation while reducing the supply voltage. The sensitivity analysis of the prescaler for various supply voltages can explain the above degradation of spectral purity. Spurious noise arises and the phase noise degrades with decreasing supply voltage due to the quasi- and non-locking operations. We verified the fully-locking operation for the LNB down-converter at a 1.4-V supply voltage.

Recent studies have focused on developing security systems using micro-Doppler radars to detect human bodies. However, the resolution of these conventional methods is unsuitable for identifying bodies and moreover, most of these conventional methods were designed for a solitary or sufficiently well-spaced targets. This paper proposes a solution to these problems with an image separation method for two closely spaced pedestrian targets. The proposed method first develops an image of the targets using ultra-wide-band (UWB) Doppler imaging radar. Next, the targets in the image are separated using a supervised learning-based separation method trained on a data set extracted using a range profile. We experimentally evaluated the performance of the image separation using some representative supervised separation methods and selected the most appropriate method. Finally, we reject false points caused by target interference based on the separation result. The experiment, assuming two pedestrians with a body separation of 0.44m, shows that our method accurately separates their images using a UWB Doppler radar with a nominal down-range resolution of 0.3m. We describe applications using various target positions, establish the performance, and derive optimal settings for our method.

Computer systems with GPUs are expected to become a strong methodology for high-speed encryption processing. Moreover, power consumption has remained a primary deterrent for such processing on devices of all sizes. However, GPU vendors are currently announcing their future roadmaps of GPU architecture development: Nvidia Corp. promotes the Kepler architecture and AMD Corp. emphasizes the GCN architecture. Therefore, we evaluated throughput and power efficiency of three 128-bit block ciphers on GPUs with recent Nvidia Kepler and AMD GCN architectures. From our experiments, whereas the throughput and per-watt throughput of AES-128 on Radeon HD 7970 (2048 cores) with GCN architecture are 205.0Gbps and 1.3Gbps/Watt respectively, those on Geforce GTX 680 (1536 cores) with Kepler architecture are, respectively, 63.9Gbps and 0.43Gbps/W; an approximately 3.2 times throughput difference occurs between AES-128 on the two GPUs. Next, we investigate the reasons for the throughput difference using our micro-benchmark suites. According to the results, we speculate that to ameliorate Kepler GPUs as co-processor of block ciphers, the arithmetic and logical instructions must be improved in terms of software and hardware.