This paper firstly presents a processor design with Derivative ASIP approach. The architecture of processor is designed by making use of a well-known embedded processor's instruction-set as a base architecture. To improve its performance, the architecture is enhanced with more hardware resources such as registers, interfaces and instruction extensions which might achieve target specifications. Secondly, a new approach for retargeting compiler by means of assembly converter tool is proposed. Our retargeting approach is practical because it is performed by the assembly converter tool with a simple configuration file and independent from a base compiler. With our proposed approach, both architecture flexibility and a good quality of assembly code can be obtained at once. Compared to other compilers, experiments show that our approach capable of generating code as high efficiency as its base compiler and the developed ASIP results in better performance than its base processor.

The Euler number of a binary image is an important topological property for pattern recognition, and can be calculated by counting certain bit-quads in the image. This paper proposes an efficient strategy for improving the bit-quad-based Euler number computing algorithm. By use of the information obtained when processing the previous bit quad, the number of times that pixels must be checked in processing a bit quad decreases from 4 to 2. Experiments demonstrate that an algorithm with our strategy significantly outperforms conventional Euler number computing algorithms.

This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189MHz, outperforms the software-based SSL protocol.

This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of Vdd and it provides 91 times better failure rate with a 35% droop of Vdd compared with the conventional design.

A soft-decision recursive decoding algorithm (RDA) for the class of the binary linear block codes recursively generated using a u|u+v-construction method is proposed. It is well known that Reed-Muller (RM) codes are in this class. A code in this class can be decomposed into left and right components. At a recursive level of the RDA, if the component is decomposable, the RDA is performed for the left component and then for the cosets generated from the left decoding result and the right component. The result of this level is obtained by concatenating the left and right decoding results. If the component is indecomposable, a proposed iterative bounded-distance decoding algorithm is performed. Computer simulations were made to evaluate the RDA for RM codes over an additive white Gaussian-noise channel using binary phase-shift keying modulation. The results show that the block error rates of the RDA are relatively close to those of the maximum-likelihood decoding for the third-order RM code of length 26 and better than those of the Chase II decoding for the third-order RM codes of length 26 and 27, and the fourth-order RM code of length 28.

This letter proposes a novel intrusion tolerant system consisting of several virtual machines (VMs) that refresh the target system periodically and by live migration, which monitors the many features of the VMs to identify and replace exhausted VMs. The proposed scheme provides adequate performance and dependability against denial of service (DoS) attacks. To show its efficiency and security, we conduct experiments on the CSIM20 simulator, which showed 22% improvement in a normal situation and approximately 77.83% improvement in heavy traffic in terms of the response time compared to that reported in the literature. We measure and compare the response time. The result show that the proposed scheme has shorter response time and maintains than other systems and supports services during the heavy traffic.

A promising application of a single-flux quantum (SFQ) circuit is read-out circuitry for a multi-channel superconductive sensor array. In such applications, the SFQ read-out circuit is expected to operate outside a magnetic shield. We investigated an SFQ circuit structure, which is tolerant to an external magnetic field, using the AIST 2.5kA/cm2 Nb standard 2 process, which has four Nb wiring layers including the ground plane. By covering the entire circuit using an upper Nb wiring layer called the control (CTL) layer, the influences of the external magnetic field on the SFQ circuit operation can be avoided. We experimentally evaluated the sheet inductance of the wiring layer underneath the CTL shielding layer to design a magnetic-field-tolerant SFQ circuit. We implemented and measured test circuits comprising toggle flip-flops (TFFs) to evaluate their magnetic field tolerances. The operating margin and maximum operating frequency of the designed TFF did not deteriorate with increases in the magnetic field applied to the test circuit, whereas the operating margin of the conventional TFF was reduced by applying the magnetic field. We have also demonstrated the high-speed operation of the designed TFF operated in an unshielded environment at a frequency of up to 120GHz with a wide operating margin.

The single flux quantum (SFQ) is expected to be a next-generation high-speed and low-power technology in the field of logic circuits. CMOS as the dominant technology for conventional processors cannot be replaced with SFQ technology due to the difficulty of implementing feedback loops and conditional branches using SFQ circuits. This paper investigates the applicability of a reconfigurable data-path (RDP) accelerator based on SFQ circuits. The authors introduce detailed specifications of the SFQ-RDP architecture and compare its performance and power/performance ratio with those of a graphics-processing unit (GPU). The results show at most 1600 times higher efficiency in terms of Flops/W (floating-point operations per second/Watt) for some high-performance computing application programs.

Gait-based owner authentication using accelerometers has recently been extensively studied owing to the development of wearable electronic devices. An actual gait signal is always subject to change due to many factors including variation of sensor attachment. In this research, we tackle to the practical sensor-orientation inconsistency, for which signal sequences are captured at different sensor orientations. We present an iterative signal matching algorithm based on phase-registration technique to simultaneously estimate relative sensor-orientation and register the 3D acceleration signals. The iterative framework is initialized by using 1D orientation-invariant resultant signals which are computed from 3D signals. As a result, the matching algorithm is robust to any initial sensor-orientation. This matching algorithm is used to match a probe and a gallery signals in the proposed owner authentication method. Experiments using actual gait signals under various conditions such as different days, sensors, weights being carried, and sensor orientations show that our authentication method achieves positive results.

This paper reports on the image compression tolerability and high implementability of a novel proposed watermarking method that uses a morphological wavelet transform based on max-plus algebra. This algorithm is suitable for embedded low-power processors in mobile devices. For objective and unified evaluation of the capability of the proposed watermarking algorithm, we focus attention on a watermarking contest presented by the IHC, which belongs to the IEICE and investigate the image quality and tolerance against JPEG compression attack. During experiments for this contest, six benchmark images processed by the proposed watermarking is done to reduce the file size of original images to 1/10, 1/20, or less, and the error rate of embedding data is reduced to 0%. Thus, the embedded data can be completely extracted. The PSNR value is up to 54.66dB in these experiments. Furthermore, when the smallest image size is attained 0.49MB and the PSNR value become about 52dB, the proposed algorithm maintains very high quality with an error rate of 0%. Additionally, the processing time of the proposed watermarking can realize about 416.4 and 4.6 times faster than that of DCT and HWT on the ARM processor, respectively. As a result, the proposed watermarking method achieves effective processing capability for mobile processors.

We propose a fast and resource-efficient agreement protocol on a request set, which is used to realize Byzantine fault tolerant server replication. Although most existing randomized protocols for Byzantine agreement exploit a modular approach, that is, a combination of agreement on a bit value and a reduction of request set values to the bit values, our protocol directly solves the multi-valued agreement problem for request sets. We introduce a novel coin tossing scheme to select a candidate of an agreed request set randomly. This coin toss allows our protocol to reduce resource consumption and to attain faster response time than the existing representative protocols.

A data-driven controller has been proposed for nonlinear systems, and its effectiveness has been also shown. However, according to this control scheme, considerable large computation burden is required in on-line learning to update the database. The on-line limit its implementation in industrial processes. In this paper, a controller design scheme is proposed, which enables us to update the database in an off-line manner.

This paper describes an analytical study of performance of a proposed signal detection scheme that will allow coexistence of an additional radio communication system (generally, secondary system) in the service area where the existing communication system (primary system) is operated. Its performance characteristics are derived by an analytical method based on stochastic theory, which is subsequently validated by software simulation. The main purpose of the detection scheme is to protect the primary system from the secondary system. In such a situation, the signals of the primary system and secondary system may be simultaneously received in the signal detector. One application of such a scheme is D-to-D (Device-to-Device) communication, whose system concept including the detection scheme is briefly introduced. For improved secondary signal detection, we propose the signal cancellation method of the primary system and the feature detection method of the secondary system signal. We evaluate the performance characteristics of the detection scheme in terms of “probability of correct detection”. We reveal that an undesired random component is produced in the feature detection procedure when two different signals are simultaneously received, which degrades the detection performance. Such undesired component is included in the analytical equations. We also clarify that the cancellation scheme improves the performance, when the power ratio of the primary signal to secondary signal is higher than 20-22dB.

As a promising lamination-loss-free fabrication technique, diffusion bonding of etched thin metal plates is used to realize double-layer waveguide slot antennas. Alternating-phase feed is adopted in this paper to reduce the number of laminated plates to simplify fabrication as well as to reduce cost. A 20 × 20-element double-layer waveguide slot antenna with a bottom partially-corporate feed circuit is designed for 39GHz band operation as an example. The adjacent radiating waveguides as well as the 2 × 2 sub-arrays fed in an alternating-phase manner eliminate the need for complete electrical contact in the top layer. However, the feed circuit in the bottom layer has to be completely diffusion-bonded. These two layers are simply assembled by screws. An antenna laminated by only diffusion bonding is also fabricated and evaluated for comparison. The comparison proved that the simply fabricated antenna is comparable in performance to the fully diffusion-bonded one.

We propose a new method that accelerates asynchronous Byzantine Fault Tolerant (BFT) protocols designed on the principle of state machine replication. State machine replication protocols ensure consistency among replicas by applying operations in the same order to all of them. A naive way to determine the application order of the operations is to repeatedly execute the BFT consensus to determine the next executed operation, but this may introduce inefficiency caused by waiting for the completion of the previous execution of the consensus protocol. To reduce this inefficiency, our method allows parallel execution of the consensuses while keeping consistency of the consensus results at the replicas. In this paper, we also prove the correctness of our method and experimentally compare it with the existing method in terms of latency and throughput. The evaluation results show that our method makes a BFT protocol three or four times faster than the existing one when some machines or message transmissions are delayed.

We propose a novel approach to the target localization problem using Doppler frequency shift measurements. We first reformulate the maximum likelihood estimation (MLE) as a constrained weighted least squares (CWLS) estimation, and then perform the semidefinite relaxation to relax the CWLS problem as a convex semidefinite programming (SDP) problem, which can be efficiently solved using modern convex optimization methods. Finally, the SDP solution can be used to initialize the original MLE which can provide estimates achieve the Cramer-Rao lower bound accuracy. Simulations corroborate the good performance of the proposed method.

In this paper, we propose a time and memory efficient Ultra Wide Band Short Range Radar (UWB SRR) system for measuring relative target velocities of up to 150km/hr. First, for the proposed detector, we select the required design parameters for good performance. The parameters are the number of coherent integrations, non-coherent integrations, and FFT points. The conventional detector uses a Fast Fourier Transform (FFT) to extract the range and velocity of the target simultaneously. Therefore, it requires high computation effort, high FFT processing time, and a huge amount of memory. However, the proposed pulse radar detector first decides the target range and then computes the target velocity using FFT sequentially for the decided range index. According to our theoretical and simulation analyses, the FFT processing time and the memory requirement are reduced compared to those of the conventional method. Finally, we show that the detection performance of the proposed detector is superior to that of the conventional detector in a background of Additive White Gaussian Noise (AWGN).

This paper presents an application of the constained interpolation profile basis set (CIP-BS) method to electromagnetic fields analyses. Electromagnetic fields can be expanded in terms of multi-dimensional CIP basis functions, and the Galerkin method can then be applied to obtain a system of linear equations. In the present study, we focus on a two-dimensional problem with TMz polarization. In order to examine the precision of the CIP-BS method, TE202 resonant mode in a rectangular cavity is analyzed. The numerical results show that CIP-BS method has better performance than the finite-difference time-domain (FDTD) method when the time step is small. Then an absorbing boundary condition based on the perfectly matched layer (PML) is formulated, and the absorption performance is demonstrated. Finally, the propagation in an inhomogeneous medium is computed by using the proposed method, and it is observed that in the CIP-BS method, smooth variation of material constants is effectively formulated without additional computational costs, and that accurate results are obtained in comparison with the FDTD method even if the permittivity is high.

Checkpoint-rollback recovery, which is a universal method for restoring distributed systems after faults, requires a sophisticated snapshot algorithm especially if the systems are large-scale, since repeatedly taking global snapshots of the whole system requires unacceptable communication cost. As a sophisticated snapshot algorithm, a partial snapshot algorithm has been introduced that takes a snapshot of a subsystem consisting only of the nodes that are communication-related to the initiator instead of a global snapshot of the whole system. In this paper, we modify the previous partial snapshot algorithm to create a new one that can take a partial snapshot more efficiently, especially when multiple nodes concurrently initiate the algorithm. Experiments show that the proposed algorithm greatly reduces the amount of communication needed for taking partial snapshots.

A virtual machine (VM) migration is useful for improving flexibility and maintainability in cloud computing environments. However, VM monitor (VMM)-bypass I/O technologies, including PCI passthrough and SR-IOV, in which the overhead of I/O virtualization can be significantly reduced, make VM migration impossible. This paper proposes a novel and practical mechanism, called Symbiotic Virtualization (SymVirt), for enabling migration and checkpoint/restart on a virtualized cluster with VMM-bypass I/O devices, without the virtualization overhead during normal operations. SymVirt allows a VMM to cooperate with a message passing layer on the guest OS, then it realizes VM-level migration and checkpoint/restart by using a combination of a user-level dynamic device configuration and coordination of distributed VMMs. We have implemented the proposed mechanism on top of QEMU/KVM and the Open MPI system. All PCI devices, including Infiniband, Ethernet, and Myrinet, are supported without implementing specific para-virtualized drivers; and it is not necessary to modify either of the MPI runtime and applications. Using the proposed mechanism, we demonstrate reactive and proactive FT mechanisms on a virtualized Infiniband cluster. We have confirmed the effectiveness using both a memory intensive micro benchmark and the NAS parallel benchmark.