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[Keyword] LER(1184hit)

181-200hit(1184hit)

  • RPE: A Seamless Redundancy Protocol for Ethernet Networks

    Nguyen Xuan TIEN  Jong Myung RHEE  

     
    PAPER-Network

      Pubricized:
    2016/11/16
      Vol:
    E100-B No:5
      Page(s):
    711-727

    High availability is crucial for industrial Ethernet networks and Ethernet-based control systems, such as automation networks and substation automation systems. Because the standard Ethernet does not support fault tolerance capability, the high availability of Ethernet networks can be increased by using redundancy protocols. Various redundancy protocols for Ethernet networks have been developed and standardized, such as rapid spanning tree protocol (RSTP), media redundancy protocol (MRP), parallel redundancy protocol (PRP), high-availability seamless redundancy (HSR), and others. RSTP and MRP provide redundancy in the network, whereas PRP and HSR provide redundancy in the end nodes. RSTP and MRP have a disadvantage in switchover delay. PRP and HSR provide zero recovery time, but PRP requires a duplicate network infrastructure, and HSR is mainly used in ring-based topologies. Additionally, PRP and HSR provide seamless redundancy in the end nodes and are applied in dedicated HSR networks with dedicated HSR nodes. In this paper, we present a novel seamless redundancy protocol for Ethernet networks, which is called the Redundancy Protocol for Ethernet (RPE). The RPE provides seamless redundancy in the network. This protocol not only provides seamless communications with zero switchover time in case of failure but also supports all topologies. The RPE is transparent and compatible with standard Ethernet nodes. These features make the RPE very useful in time-critical and mission-critical systems, such as substation automation systems, automation networks, and other industrial Ethernet networks.

  • A Survey of Efficient Ray-Tracing Techniques for Mobile Radio Propagation Analysis Open Access

    Tetsuro IMAI  

     
    INVITED SURVEY PAPER-Antennas and Propagation

      Pubricized:
    2016/12/01
      Vol:
    E100-B No:5
      Page(s):
    666-679

    With the advances in computer processing that have yielded an enormous increase in performance, numerical analytical approaches based on electromagnetic theory have recently been applied to mobile radio propagation analysis. One such approach is the ray-tracing method based on geometrical optics and the uniform geometrical theory of diffraction. In this paper, ray-tracing techniques that have been proposed in order to improve computational accuracy and speed are surveyed. First, imaging and ray-launching methods are described and their extended methods are surveyed as novel fundamental ray-tracing techniques. Next, various ray-tracing acceleration techniques are surveyed and categorized into three approaches, i.e., deterministic, heuristic, and brute force. Then, hybrid methods are surveyed such as those employing Physical optics, the Effective Roughness model, and the Finite-Difference Time-Domain method that have been proposed in order to improve analysis accuracy.

  • A Fast and Accurate FPGA System for Short Read Mapping Based on Parallel Comparison on Hash Table

    Yoko SOGABE  Tsutomu MARUYAMA  

     
    PAPER-Computer System

      Pubricized:
    2017/01/30
      Vol:
    E100-D No:5
      Page(s):
    1016-1025

    The purpose of DNA sequencing is to determine the order of nucleotides within a DNA molecule of target. The target DNA molecules are fragmented into short reads, which are short fixed-length subsequences composed of ‘A’, ‘C’, ‘G’ ‘T’, by next generation sequencing (NGS) machine. To reconstruct the target DNA from the short reads using a reference genome, which is a representative example of a species that was constructed in advance, it is necessary to determine their locations in the target DNA from where they have been extracted by aligning them onto the reference genome. This process is called short read mapping, and it is important to improve the performance of the short read mapping to realize fast DNA sequencing. We propose three types of FPGA acceleration methods based on hash table; (1) sorting and parallel comparison, (2) matching that allows one mutation to reduce the number of the candidates, (3) optimized hash function using variable masks. The first one reduces the number of accesses to off-chip memory to avoid the bottleneck by access latency. The second one enables to reduce the number of the candidates without degrading mapping sensitivity by allowing one mutation in the comparison. The last one reduces hash collisions using a table that was calculated from the reference genome in advance. We implemented the three methods on Xilinx Virtex-7 and evaluated them to show their effectiveness of them. In our experiments, our system achieves 20 fold of processing speed compared with BWA, which is one of the most popular mapping tools. Furthermore, we shows that the our system outperforms one of the fastest FPGA short read mapping systems.

  • Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA

    Makoto SAEN  Tadanobu TOBA  Yusuke KANNO  

     
    PAPER

      Vol:
    E100-C No:4
      Page(s):
    382-390

    This paper presents a soft-error-tolerant memory-control circuit for SRAM-based field programmable gate arrays (FPGAs). A potential obstacle to applying such FPGAs to safety-critical industrial control systems is their low tolerance. The main reason is that soft errors damage circuit-configuration data stored in SRAM-based configuration memory. To overcome this obstacle, the soft-error tolerance must thus be improved while suppressing the circuit area overhead, and data stored in external memory must be protected when a fault occurs on the FPGA. Therefore, a memory-control circuit was developed on the basis of a dual-modular-redundancy (DMR) architecture. This memory controller has a repair and retry scheme that repairs damaged circuit-configuration data and re-executes unfinished accesses after the repair. The developed architecture reduces circuit redundancy below that of a commonly used triple-modular-redundancy (TMR) architecture. Moreover, a write-invalidation circuit was developed to protect data in external memory, and an external-memory-state recovery circuit was developed to enable resumption of memory access after fault repair. The developed memory controller was implemented in a prototype circuit on an FPGA and evaluated using the prototype. The evaluation results demonstrated that the developed memory controller can operate successfully for 1.03×109 hours (at sea level). In addition, its circuit area overhead was found to be sufficiently smaller than that of the TMR architecture.

  • An Effective and Simple Solution for Stationary Target Localization Using Doppler Frequency Shift Measurements

    Li Juan DENG  Ping WEI  Yan Shen DU  Wan Chun LI  Ying Xiang LI  Hong Shu LIAO  

     
    LETTER-Digital Signal Processing

      Vol:
    E100-A No:4
      Page(s):
    1070-1073

    Target determination based on Doppler frequency shift (DFS) measurements is a nontrivial problem because of the nonlinear relation between the position space and the measurements. The conventional methods such as numerical iterative algorithm and grid searching are used to obtain the solution, while the former requires an initial position estimate and the latter needs huge amount of calculations. In this letter, to avoid the problems appearing in those conventional methods, an effective solution is proposed, in which two best linear unbiased estimators (BULEs) are employed to obtain an explicit solution of the proximate target position. Subsequently, this obtained explicit solution is used to initialize the problem of original maximum likelihood estimation (MLE), which can provide a more accurate estimate.

  • Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core Open Access

    Motoki AMAGASAKI  Yuki NISHITANI  Kazuki INOUE  Masahiro IIDA  Morihiro KUGA  Toshinori SUEYOSHI  

     
    INVITED PAPER

      Pubricized:
    2017/01/13
      Vol:
    E100-D No:4
      Page(s):
    633-644

    Fault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area.

  • Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip

    Ruilian XIE  Jueping CAI  Xin XIN  Bo YANG  

     
    LETTER-Computer System

      Pubricized:
    2017/01/20
      Vol:
    E100-D No:4
      Page(s):
    910-913

    This letter presents a Preferable Mad-y (PMad-y) turn model and Low-cost Adaptive and Fault-tolerant Routing (LAFR) method that use one and two virtual channels along the X and Y dimensions for 2D mesh Network-on-Chip (NoC). Applying PMad-y rules and using the link status of neighbor routers within 2-hops, LAFR can tolerate multiple faulty links and routers in more complicated faulty situations and impose the reliability of network without losing the performance of network. Simulation results show that LAFR achieves better saturation throughput (0.98% on average) than those of other fault-tolerant routing methods and maintains high reliability of more than 99.56% on average. For achieving 100% reliability of network, a Preferable LAFR (PLAFR) is proposed.

  • FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm

    Henry BLOCK  Tsutomu MARUYAMA  

     
    PAPER-Computer System

      Pubricized:
    2016/11/14
      Vol:
    E100-D No:2
      Page(s):
    256-264

    In this paper, we present an FPGA hardware implementation for a phylogenetic tree reconstruction with a maximum parsimony algorithm. We base our approach on a particular stochastic local search algorithm that uses the Progressive Neighborhood and the Indirect Calculation of Tree Lengths method. This method is widely used for the acceleration of the phylogenetic tree reconstruction algorithm in software. In our implementation, we define a tree structure and accelerate the search by parallel and pipeline processing. We show results for eight real-world biological datasets. We compare execution times against our previous hardware approach, and TNT, the fastest available parsimony program, which is also accelerated by the Indirect Calculation of Tree Lengths method. Acceleration rates between 34 to 45 per rearrangement, and 2 to 6 for the whole search, are obtained against our previous hardware approach. Acceleration rates between 2 to 36 per rearrangement, and 18 to 112 for the whole search, are obtained against TNT.

  • An Efficient Soft Shadow Mapping for Area Lights in Various Shapes and Colors

    Youngjae CHUN  Kyoungsu OH  

     
    LETTER-Computer Graphics

      Pubricized:
    2016/11/11
      Vol:
    E100-D No:2
      Page(s):
    396-400

    Shadow is an important effect that makes virtual 3D scenes more realistic. In this paper, we propose a fast and correct soft shadow generation method for area lights of various shapes and colors. To conduct efficient as well as accurate visibility tests, we exploit the complexity of shadow and area light color.

  • A Study on Adaptive Scheduling Priority Control for Layered Cell Configuration

    Atsushi NAGATE  Teruya FUJII  Masayuki MURATA  

     
    PAPER-Terrestrial Wireless Communication/Broadcasting Technologies

      Pubricized:
    2016/09/15
      Vol:
    E100-B No:2
      Page(s):
    372-379

    The layered cell configuration, in which a large number of small cells are set in a macro-cell coverage area, is attracting much attention recently as a promising approach to handle the rapidly increasing mobile data traffic. In this configuration, cells of various sizes, from macro to small, are placed in various locations, so that the variation in the number and the distribution of the users among cells becomes much wider than in conventional macro-cell homogeneous networks. Therefore, even in the layered cell configuration, the users in the cell with many users and low received signal quality may experience low throughput especially at cell edge. This is because such users experience both low spectral efficiency and few radio resources. In order to resolve this issue, a lot of techniques have been proposed such as load balancing and cooperative multi-point transmission. In this paper, we focus on scheduling priority control as a simple solution that can also be used in combination with load balancing and coordinated multi-point transmission. We propose an adaptive scheduling priority control scheme based on the congestion and user distribution of each cell and clarify the effect of the proposed method by computer simulations.

  • Advances in Analog-to-Digital Converters over the Last Decade

    Sanroku TSUKAMOTO  

     
    INVITED PAPER

      Vol:
    E100-A No:2
      Page(s):
    524-533

    As the scaling of CMOS technology advances, the characteristics of transistors are evolving toward digital circuit design. This means conventional analog design techniques are getting harder to apply to advanced technology, because of the low power supply voltage, narrow dynamic range of switching properties, and low trans-conductance of transistors. Despite such circumstances, analog-to-digital converter (ADC) performance is still advancing, thanks to innovative new architectures. This paper reviews the recent trend of ADCs, exploring their performance as well as use of the time interleave scheme, non-static current amplifiers, and hybrid architectures.

  • An Improved Controller Area Network Data-Reduction Algorithm for In-Vehicle Networks

    Yujing WU  Jin-Gyun CHUNG  

     
    PAPER

      Vol:
    E100-A No:2
      Page(s):
    346-352

    As the number of electronic control units (ECUs) or sensors connected to a controller area network (CAN) bus increases, so does the bus load. When a CAN bus is overloaded by a large number of ECUs, both the waiting time and the error probability of the data transmission are increased. Because the duration of the data transmission is proportional to the frame length, it is desirable to reduce the CAN frame length. In this paper, we present an improved CAN data-reduction (DR) algorithm to reduce the amount of data to be transferred in the CAN frame length. We also implement the data reduction algorithm using the CANoe software, and measure the CAN bus load using a CANcaseXL device. Experimental results with a Kia Sorento vehicle indicate that we can obtain additional average compression ratio of 11.15% with the proposed method compared with the ECANDC algorithm. By using the CANoe software, we show that the average message delay is within 0.10ms and the bus load can be reduced by 23.45% with 20 ECUs using the proposed method compared with the uncompressed message.

  • A Weil Pairing on a Family of Genus 2 Hyperelliptic Curves with Efficiently Computable Automorphisms

    Masahiro ISHII  Atsuo INOMATA  Kazutoshi FUJIKAWA  

     
    PAPER

      Vol:
    E100-A No:1
      Page(s):
    62-72

    In this paper, we provided a new variant of Weil pairing on a family of genus 2 curves with the efficiently computable automorphism. Our pairing can be considered as a generalization of the omega pairing given by Zhao et al. We also report the algebraic cost estimation of our pairing. We then show that our pairing is more efficient than the variant of Tate pairing with the automorphism given by Fan et al. Furthermore, we show that our pairing is slightly better than the twisted Ate pairing on Kawazoe-Takahashi curve at the 192-bit security level.

  • Designing and Implementing a Diversity Policy for Intrusion-Tolerant Systems

    Seondong HEO  Soojin LEE  Bumsoon JANG  Hyunsoo YOON  

     
    PAPER-Dependable Computing

      Pubricized:
    2016/09/29
      Vol:
    E100-D No:1
      Page(s):
    118-129

    Research on intrusion-tolerant systems (ITSs) is being conducted to protect critical systems which provide useful information services. To provide services reliably, these critical systems must not have even a single point of failure (SPOF). Therefore, most ITSs employ redundant components to eliminate the SPOF problem and improve system reliability. However, systems that include identical components have common vulnerabilities that can be exploited to attack the servers. Attackers prefer to exploit these common vulnerabilities rather than general vulnerabilities because the former might provide an opportunity to compromise several servers. In this study, we analyze software vulnerability data from the National Vulnerability Database (NVD). Based on the analysis results, we present a scheme that finds software combinations that minimize the risk of common vulnerabilities. We implement this scheme with CSIM20, and simulation results prove that the proposed scheme is appropriate for a recovery-based intrusion tolerant architecture.

  • Recommendation-Based Bandwidth Calendaring for Packet Transport Network

    Shohei KAMAMURA  Rie HAYASHI  Hiroki DATE  Hiroshi YAMAMOTO  Takashi MIYAMURA  Yoshihiko UEMATSU  Kouichi GENDA  

     
    PAPER-Network

      Pubricized:
    2016/08/04
      Vol:
    E100-B No:1
      Page(s):
    122-130

    This paper proposes a recommendation-based bandwidth calendaring system for packet transport networks. The system provides a user-portal interface with which users can directly reserve packet transport resources. In this regard, the system recommends multi-grade (e.g., multi-price) reservation plans. By adjusting grades of plans in accordance with network resource utilization, this system provides not only reservation flexibility for users but also efficient utilization of network resources. For recommending multi-grade plans, pre-computation of resource allocation is required for every time slot. Because the number of time slots is huge, we also propose an algorithm for fast computation of resource allocation based on time-slot aggregation. Our evaluation suggests that our algorithm can produce a sub-optimal solution within quasi-real time for a large-scale network. We also show that our recommendation-based system can increase the service-provider-revenue in peaky traffic demand environments.

  • Delay-Tolerable Contents Offloading via Vehicular Caching Overlaid with Cellular Networks

    Byoung-Yoon MIN  Wonkwang SHIN  Dong Ku KIM  

     
    PAPER-Mobile Information Network and Personal Communications

      Vol:
    E100-A No:1
      Page(s):
    283-293

    Wireless caching is one of the promising technologies to mitigate the traffic burden of cellular networks and the large cost of deploying a higher volume of wired backhaul by introducing caching storage. In the manner of “cutting” wired equipments, all types of vehicles can be readily leveraged as serving access points with caching storage, where their moving nature should be taken into account to improve latency and data throughput. In this paper, we consider a mobility-aware vehicular caching which has a role in offloading delay-tolerable contents from cellular networks. We first clarify the influence of mobility in cellular caching networks, then set the mobility-aware optimization problem of vehicular caching to carry on delay-tolerable contents. Trace-driven numerical results based on rural and urban topographies show that, in presence of individual demand for delay-tolerable contents, the proposed vehicular caching scheme enhances the quality-of-service (QoS) (maximally twofold) relying on the contents delivery being centrally or distributedly controlled.

  • Towards Practical Store-Carry-Forward Networking: Examples and Issues Open Access

    Masato TSURU  Mineo TAKAI  Shigeru KANEDA   Agussalim  Rabenirina AINA TSIORY  

     
    INVITED PAPER-Network

      Vol:
    E100-B No:1
      Page(s):
    2-10

    In the evolution of wireless networks such as wireless sensor networks, mobile ad-hoc networks, and delay/disruption tolerant networks, the Store-Carry-Forward (SCF) message relaying paradigm has been commonly featured and studied with much attention. SCF networking is essential for offsetting the deficiencies of intermittent and range limited communication environments because it allows moving wireless communication nodes to act as “mobile relay nodes”. Such relay nodes can store/carry/process messages, wait for a better opportunity for transmission, and finally forward the messages to other nodes. This paper starts with a short overview of SCF routing and then examines two SCF networking scenarios. The first one deals with large content delivery across multiple islands using existing infrastructural transportation networks (e.g., cars and ferries) in which mobility is uncontrollable from an SCF viewpoint. Simulations show how a simple coding technique can improve flooding-based SCF. The other scenario looks at a prototype system of unmanned aerial vehicle (UAV) for high-quality video surveillance from the sky in which mobility is partially controllable from an SCF viewpoint. Three requisite techniques in this scenario are highlighted - fast link setup, millimeter wave communications, and use of multiple links. Through these examples, we discuss the benefits and issues of the practical use of SCF networking-based systems.

  • Initial Value Problem Formulation TDBEM with 4-D Domain Decomposition Method and Application to Wake Fields Analysis

    Hideki KAWAGUCHI  Thomas WEILAND  

     
    PAPER

      Vol:
    E100-C No:1
      Page(s):
    37-44

    The Time Domain Boundary Element Method (TDBEM) has its advantages in the analysis of transient electromagnetic fields (wake fields) induced by a charged particle beam with curved trajectory in a particle accelerator. On the other hand, the TDBEM has disadvantages of huge required memory and computation time compared with those of the Finite Difference Time Domain (FDTD) method or the Finite Integration Technique (FIT). This paper presents a comparison of the FDTD method and 4-D domain decomposition method of the TDBEM based on an initial value problem formulation for the curved trajectory electron beam, and application to a full model simulation of the bunch compressor section of the high-energy particle accelerators.

  • Home Base-Aware Store-Carry-Forward Routing Using Location-Dependent Utilities of Nodes

    Tomotaka KIMURA  Yutsuki KAYAMA  Tetsuya TAKINE  

     
    PAPER-Network

      Vol:
    E100-B No:1
      Page(s):
    17-27

    We propose a home base-aware store-carry-forward routing scheme using location-dependent utilities of nodes, which adopts different message forwarding strategies depending on location where nodes encounter. Our routing scheme first attempts to deliver messages to its home base, the area with the highest potential for the presence of the destination node in the near future. Once a message copy reaches its home base, message dissemination is limited within the home base, and nodes with message copies wait for encountering the destination node. To realize our routing scheme, we use two different utilities of nodes depending on location: Outside the home base of a message, nodes approaching to the home base have high utility values, while within the home base, nodes staying the home base have high utility values. By using these utilities properly, nodes with message copies will catch the destination node “by ambush” in the home base of the destination node. Through simulation experiments, we demonstrate the effectiveness of our routing scheme.

  • Energy Efficient Information Retrieval for Content Centric Networks in Disaster Environment

    Yusaku HAYAMIZU  Tomohiko YAGYU  Miki YAMAMOTO  

     
    PAPER

      Vol:
    E99-B No:12
      Page(s):
    2509-2519

    Communication infrastructures under the influence of the disaster strike, e.g., earthquake, will be partitioned due to the significant damage of network components such as base stations. The communication model of the Internet bases on a location-oriented ID, i.e., IP address, and depends on the DNS (Domain Name System) for name resolution. Therefore such damage remarkably deprives the reachability to the information. To achieve robustness of information retrieval in disaster situation, we try to apply CCN/NDN (Content-Centric Networking/Named-Data Networking) to information networks fragmented by the disaster strike. However, existing retransmission control in CCN is not suitable for the fragmented networks with intermittent links due to the timer-based end-to-end behavior. Also, the intermittent links cause a problem for cache behavior. In order to resolve these technical issues, we propose a new packet forwarding scheme with the dynamic routing protocol which resolves retransmission control problem and cache control scheme suitable for the fragmented networks. Our simulation results reveal that the proposed caching scheme can stably store popular contents into cache storages of routers and improve cache hit ratio. And they also reveal that our proposed packet forwarding method significantly improves traffic load, energy consumption and content retrieval delay in fragmented networks.

181-200hit(1184hit)