In frequency hopping communication, time delay and Doppler shift incur interference. With the escalating upgrading of complicated interference, in this paper, the time-frequency two-dimensional (TFTD) partial Hamming correlation (PHC) properties of wide-gap frequency-hopping sequences (WGFHSs) with frequency shift are discussed. A bound on the maximum TFTD partial Hamming auto-correlation (PHAC) and two bounds on the maximum TFTD PHC of WGFHSs are got. Li-Fan-Yang bounds are the particular cases of new bounds for frequency shift is zero.

The orthogonal time frequency space (OTFS) technique proposed in recent years has excellent anti-Doppler frequency shift and time delay performance, enabling its application in high speed communication scenarios. In this article, a particle swarm optimization (PSO) signal detection algorithm for OTFS system is proposed, an adaptive mechanism for the individual learning factor and global learning factor in the speed formula of the algorithm is designed, and the position update method of the particles is improved, so as to increase the convergence accuracy and avoid the particles to fall into local optimum. The simulation results show that the improved PSO algorithm has the advantages of low bit error rate (BER) and high convergence accuracy compared with the traditional PSO algorithm, and has similar performance to the ideal state maximum likelihood (ML) detection algorithm with lower complexity. In the case of high Doppler shift, OTFS technology has better performance than orthogonal frequency division multiplexing (OFDM) technology by using improved PSO algorithm.

Previously, convolutional neural networks have made tremendous progress in target recognition based on micro-Doppler radar. However, these studies only considered the presence of one target at a time in the surveillance area. Simultaneous multi-targets recognition for surveillance radar remains a pretty challenging issue. To alleviate this issue, this letter develops a multi-instance multi-label (MIML) learning strategy, which can automatically locate the crucial input patterns that trigger the labels. Benefitting from its powerful target-label relation discovery ability, the proposed framework can be trained with limited supervision. We emphasize that only echoes from single targets are involved in training data, avoiding the preparation and annotation of multi-targets echo in the training stage. To verify the validity of the proposed method, we model two representative ground moving targets, i.e., person and wheeled vehicles, and carry out numerous comparative experiments. The result demonstrates that the developed framework can simultaneously recognize multiple targets and is also robust to variation of the signal-to-noise ratio (SNR), the initial position of targets, and the difference in scattering coefficient.

As ransomware inevitably overwrites existing data, SSDs can detect ransomware attacks by monitoring overwrites. The state-of-the-art technology uses a hash to monitor overwrites, which consumes tens of bytes of memory per I/O. To improve memory efficiency, we propose a bitmap-based overwrite detection method that uses only one bit per I/O.

It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5µsec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.

Many deep convolutional neural network (CNN) inference accelerators on the field-programmable gate array (FPGA) platform have been widely adopted due to their low power consumption and high performance. In this paper, we develop the following to improve performance and power efficiency. First, we use a high bandwidth memory (HBM) to expand the bandwidth of data transmission between the off-chip memory and the accelerator. Second, a fully-pipelined manner, which consists of pipelined inter-layer computation and a pipelined computation engine, is implemented to decrease idle time among layers. Third, a multi-core architecture with shared-dual buffers is designed to reduce off-chip memory access and maximize the throughput. We designed the proposed accelerator on the Xilinx Alveo U280 platform with in-depth Verilog HDL instead of high-level synthesis as the previous works and explored the VGG-16 model to verify the system during our experiment. With a similar accelerator architecture, the experimental results demonstrate that the memory bandwidth of HBM is 13.2× better than DDR4. Compared with other accelerators in terms of throughput, our accelerator is 1.9×/1.65×/11.9× better than FPGA+HBM2 based/low batch size (4) GPGPU/low batch size (4) CPU. Compared with the previous DDR+FPGA/DDR+GPGPU/DDR+CPU based accelerators in terms of power efficiency, our proposed system provides 1.4-1.7×/1.7-12.6×/6.6-37.1× improvement with the large-scale CNN model.

In quasi-synchronous FH multiple-access (QS-FHMA) systems, no-hit-zone frequency-hopping sequences (NHZ-FHSs) can offer interference-free FHMA performance. But, outside the no-hit-zone (NHZ), the Hamming correlation of traditional NHZ-FHZs maybe so large that the performance becomes not good. And in high-speed mobile environment, Doppler shift phenomenon will appear. In order to ensure the performance of FHMA, it is necessary to study the NHZ-FHSs in the presence of transmission delay and frequency offset. In this paper, We derive a lower bound on the maximum time-frequency two-dimensional Hamming correlation outside of the NHZ of NHZ-FHSs. The Zeng-Zhou-Liu-Liu bound is a particular situation of the new bound for frequency shift is zero.

The acquisition of distant sound has always been a hot research topic. Since sound is caused by vibration, one of the best methods for measuring distant sound is to use a laser Doppler vibrometer (LDV). This laser has high directivity, that enables it to acquire sound from far away, which is of great practical use for disaster relief and other situations. However, due to the vibration characteristics of the irradiated object itself and the reflectivity of its surface (or other reasons), the acquired sound is often lacking frequency components in certain frequency bands and is mixed with obvious noise. Therefore, when using LDV to acquire distant speech, if we want to recognize the actual content of the speech, it is necessary to enhance the acquired speech signal in some way. Conventional speech enhancement methods are not generally applicable due to the various types of degradation in observed speech. Moreover, while several speech enhancement methods for LDV have been proposed, they are only effective when the irradiated object is known. In this paper, we present a speech enhancement method for LDV that can deal with unknown irradiated objects. The proposed method is composed of noise reduction, pitch detection, power spectrum envelope estimation, power spectrum reconstruction, and phase estimation. Experimental results demonstrate the effectiveness of our method for enhancing the acquired speech with unknown irradiated objects.

Pseudorandom sequences with large linear complexity can resist the linear attack. The trace representation plays an important role in analysis and design of pseudorandom sequences. In this letter, we present the construction of a family of new binary sequences derived from Euler quotients modulo pq, where pq is a product of two primes and p divides q-1. Firstly, the linear complexity of the sequences are investigated. It is proved that the sequences have larger linear complexity and can resist the attack of Berlekamp-Massey algorithm. Then, we give the trace representation of the proposed sequences by determining the corresponding defining pair. Moreover, we generalize the result to the Euler quotients modulo pmqn with m≤n. Results indicate that the generalized sequences still have high linear complexity. We also give the trace representation of the generalized sequences by determining the corresponding defining pair. The result will be helpful for the implementation and the pseudorandom properties analysis of the sequences.

In a practical classification problem, there are cases where incorrect labels are included in training data due to label noise. We introduce a classification method in the presence of label noise that idealizes a classification method based on the expectation-maximization (EM) algorithm, and evaluate its performance theoretically. Its performance is asymptotically evaluated by assessing the risk function defined as the Kullback-Leibler divergence between predictive distribution and true distribution. The result of this performance evaluation enables a theoretical evaluation of the most successful performance that the EM-based classification method may achieve.

The approximate logarithmic multiplier proposed by Mitchell provides an efficient alternative for processing dense multiplication or multiply-accumulate operations in applications such as image processing and real-time robotics. It offers the advantages of small area, high energy efficiency and is suitable for applications that do not necessarily achieve high accuracy. However, its maximum error of 11.1% makes it challenging to deploy in applications requiring relatively high accuracy. This paper proposes a novel operand decomposition method (OD) that decomposes one multiplication into the sum of multiple approximate logarithmic multiplications to widely reduce Mitchell multiplier errors while taking full advantage of its area savings. Based on the proposed OD method, this paper also proposes an accuracy reconfigurable multiply-accumulate (MAC) unit that provides multiple reconfigurable accuracies with high parallelism. Compared to a MAC unit consisting of accurate multipliers, the area is significantly reduced to less than half, improving the hardware parallelism while satisfying the required accuracy for various scenarios. The experimental results show the excellent applicability of our proposed MAC unit in image smoothing and robot localization and mapping application. We have also designed a prototype processor that integrates the minimum functionality of this MAC unit as a vector accelerator and have implemented a software-level accuracy reconfiguration in the form of an instruction set extension. We experimentally confirmed the correct operation of the proposed vector accelerator, which provides the different degrees of accuracy and parallelism at the software level.

From edge devices to cloud servers, providing optimized hardware acceleration for specific applications has become a key approach to improve the efficiency of computer systems. Traditionally, many systems employ commercial field-programmable gate arrays (FPGAs) to implement dedicated hardware accelerator as the CPU's co-processor. However, commercial FPGAs are designed in generic architectures and are provided in the form of discrete chips, which makes it difficult to meet increasingly diversified market needs, such as balancing reconfigurable hardware resources for a specific application, or to be integrated into a customer's system-on-a-chip (SoC) in the form of embedded FPGA (eFPGA). In this paper, we propose an eFPGA generation suite with customizable architecture and integrated development environment (IDE), which covers the entire eFPGA design generation, testing, and utilization stages. For the eFPGA design generation, our intellectual property (IP) generation flow can explore the optimal logic cell, routing, and array structures for given target applications. For the testability, we employ a previously proposed shipping test method that is 100% accurate at detecting all stuck-at faults in the entire FPGA-IP. In addition, we propose a user-friendly and customizable Web-based IDE framework for the generated eFPGA based on the NODE-RED development framework. In the case study, we show an eFPGA architecture exploration example for a differential privacy encryption application using the proposed suite. Then we show the implementation and evaluation of the eFPGA prototype with a 55nm test element group chip design.

We attempt to design and fabricate of a 4×4 Butler matrix for short-millimeter-wave frequencies by using the microfabrication process for a polytetrafluoroethylene (PTFE) substrate-integrated waveguide (SIW) by the synchrotron radiation (SR) direct etching of PTFE and the addition of a metal film by sputter deposition. First, the dimensions of the PTFE SIW using rectangular through-holes for G-band (140-220 GHz) operation are determined, and a cruciform 90 ° hybrid coupler and an intersection circuit are connected by the PTFE SIW to design the Butler matrix. Then, a trial fabrication is performed. Finally, the validity of the design result and the fabrication process is verified by measuring the radiation pattern.

With the development of network technology, next-generation networks must satisfy many new requirements for network functions and performance. The processing of overlong packet fields is one of the requirements and is also the basis for ID-based routing and content lookup, and packet field addition/deletion mechanisms. The current SDN switches do not provide good support for the processing of overlong fields. In this paper, we propose a series of optimization mechanisms for protocol-oblivious instructions, in which we address the problem of insufficient support for overlong data in existing SDN switches by extending the bit width of instructions and accelerating them using SIMD instruction sets. We also provide an intermediate representation of the protocol-oblivious instruction set to improve the efficiency of storing and reading instruction blocks, and further reduce the execution time of instruction blocks by preprocessing them. The experiments show that our approach improves the performance of overlong data processing by 56%. For instructions involving packet field addition and deletion, the improvement in performance reaches 455%. In normal forwarding scenarios, our solution reduces the packet forwarding latency by around 30%.

In this study, we propose an accurate range-Doppler analysis algorithm for moving multiple objects in a short range using microwave (including millimeter wave) radars. As a promising Doppler analysis for the above model, we previously proposed a weighted kernel density (WKD) estimator algorithm, which overcomes several disadvantages in coherent integration based methods, such as a trade-off between temporal and frequency resolutions. However, in handling multiple objects like human body, it is difficult to maintain the accuracy of the Doppler velocity estimation, because there are multiple responses from multiple parts of object, like human body, incurring inaccuracies in range or Doppler velocity estimation. To address this issue, we propose an iterative algorithm by exploiting an output of the WKD algorithm. Three-dimensional numerical analysis, assuming a human body model in motion, and experimental tests demonstrate that the proposed algorithm provides more accurate, high-resolution range-Doppler velocity profiles than the original WKD algorithm, without increasing computational complexity. Particularly, the simulation results show that the cumulative probabilities of range errors within 10mm, and Doppler velocity error within 0.1m/s are enhanced from 34% (by the former method) to 63% (by the proposed method).

A waveguide 2-plane hybrid coupler with two operating bands is proposed. The cross-sectional shape of the coupled region inside the proposed coupler is designed with a two-dimensional arbitrary geometry sorting method. Simulations of the proposed hybrid coupler has a fractional bandwidth (FBW) of 2.17% at the center of 24.99GHz, and at the center of 28.28GHz an FBW of 6.13%. The proposed coupler is analyzed by the mode-matching finite-element hybrid method, and the final result is obtained using a genetic algorithm. The analyzed result of the coupling for the main modes in the coupled region is presented. The design result is confirmed by measurements.

Multilayer perceptron (MLP) is a basic neural network model that is used in practical industrial applications, such as network intrusion detection (NID) systems. It is also used as a building block in newer models, such as gMLP. Currently, there is a demand for fast training in NID and other areas. However, in training with numerous GPUs, the problems of power consumption and long training times arise. Many of the latest deep neural network (DNN) models and MLPs are trained using a backpropagation algorithm which transmits an error gradient from the output layer to the input layer such that in the sequential computation, the next input cannot be processed until the weights of all layers are updated from the last layer. This is known as backward locking. In this study, a weight parameter update mechanism is proposed with time delays that can accommodate the weight update delay to allow simultaneous forward and backward computation. To this end, a one-dimensional systolic array structure was designed on a Xilinx U50 Alveo FPGA card in which each layer of the MLP is assigned to a processing element (PE). The time-delay backpropagation algorithm executes all layers in parallel, and transfers data between layers in a pipeline. Compared to the Intel Core i9 CPU and NVIDIA RTX 3090 GPU, it is 3 times faster than the CPU and 2.5 times faster than the GPU. The processing speed per power consumption is 11.5 times better than that of the CPU and 21.4 times better than that of the GPU. From these results, it is concluded that a training accelerator on an FPGA can achieve high speed and energy efficiency.

In this letter, a path dynamics assessment asynchronous advantage actor-critic scheduling algorithm (PDAA3C) is proposed to solve the MPTCP scheduling problem by using deep reinforcement learning Actor-Critic framework. The algorithm picks out the optimal transmitting path faster by multi-core asynchronous updating and also guarantee the network fairness. Compared with the existing algorithms, the proposed algorithm achieves 8.6% throughput gain over RLDS algorithm, and approaches the theoretic upper bound in the NS3 simulation.

Deep Neural Network (DNN) is widely used for computer vision tasks, such as image classification, object detection, and segmentation. DNN accelerator on FPGA and especially Convolutional Neural Network (CNN) is a hot topic. More research and education should be conducted to boost this field. A starting point is required to make it easy for new entrants to join this field. We believe that FPGA-based Autonomous Driving (AD) motor cars are suitable for this because DNN accelerators can be used for image processing with low latency. In this paper, we propose an FPGA-based simple and open-source mini motor car system named RVCar with a RISC-V soft processor and a CNN accelerator. RVCar is suitable for the new entrants who want to learn the implementation of a CNN accelerator and the surrounding system. The motor car consists of Xilinx Nexys A7 board and simple parts. All modules except the CNN accelerator are implemented in Verilog HDL and SystemVerilog. The CNN accelerator is converted from a PyTorch model by our tool. The accelerator is written in C++, synthesizable by Vitis HLS, and an easy-to-customize baseline for the new entrants. FreeRTOS is used to implement AD algorithms and executed on the RISC-V soft processor. It helps the users to develop the AD algorithms efficiently. We conduct a case study of the simple AD task we define. Although the task is simple, it is difficult to achieve without image recognition. We confirm that RVCar can recognize objects and make correct decisions based on the results.

Machine-to-Machine (M2M) communication plays a pivotal role in the evolution of Internet of Things (IoT). Cellular networks are considered to be a key enabler for M2M communications, which are originally designed mainly for Human-to-Human (H2H) communications. The introduction of M2M users will cause a series of problems to traditional H2H users, i.e., interference between various traffic. Resource allocation is an effective solution to these problems. In this paper, we consider a shared resource block (RB) and power allocation in an H2H/M2M coexistence scenario, where M2M users are subdivided into delay-tolerant and delay-sensitive types. We first model the RB-power allocation problem as maximization of capacity under Quality-of-Service (QoS) constraints of different types of traffic. Then, a learning framework is introduced, wherein a complex agent is built from simpler subagents, which provides the basis for distributed deployment scheme. Further, we proposed distributed Q-learning based autonomous RB-power allocation algorithm (DQ-ARPA), which enables the machine type network gateways (MTCG) as agents to learn the wireless environment and choose the RB-power autonomously to maximize M2M pairs' capacity while ensuring the QoS requirements of critical services. Simulation results indicates that with an appropriate reward design, our proposed scheme succeeds in reducing the impact of delay-tolerant machine type users on critical services in terms of SINR thresholds and outage ratios.