This paper proposes fast repairing methods that uses hierarchical software defined network controllers for recovering from massive failure in a large-scale IP over a wavelength-division multiplexing network. The network consists of multiple domains, and slave controllers are deployed in each domain. While each slave controller configures transport paths in its domain, the master controller manages end-to-end paths, which are established across multiple domains. For fast repair of intra-domain paths by the slave controllers, we define the optimization problem of path configuration order and propose a heuristic method, which minimizes the repair time to move from a disrupted state to a suboptimal state. For fast repair of end-to-end path through multiple domains, we also propose a network abstraction method, which efficiently manages the entire network. Evaluation results suggest that fast repair within a few minutes can be achieved by applying the proposed methods to the repairing scenario, where multiple links and nodes fail, in a 10,000-node network.

When there are multiple component predictors, it is promising to integrate them into one predictor for advanced reasoning. If each component predictor is given as a stochastic model in the form of probability distribution, an exponential mixture of the component probability distributions provides a good way to integrate them. However, weight parameters used in the exponential mixture model are difficult to estimate if there is no training samples for performance evaluation. As a suboptimal way to solve this problem, weight parameters may be estimated so that the exponential mixture model should be a balance point that is defined as an equilibrium point with respect to the distance from/to all component probability distributions. In this paper, we propose a weight parameter estimation method that represents this concept using a symmetric Kullback-Leibler divergence and generalize this method.

In a multi-tenant data center, nodes and links of tenants' virtual networks (VNs) share a single component of the physical substrate network (SN). The failure of a single SN component can thereby cause the simultaneous failures of multiple nodes and links in a single VN; this complex of failures must significantly disrupt the services offered on the VN. In the present paper, we clarify how the fault tolerance of each VN is affected by a single SN failure, especially from the perspective of VN allocation in the SN. We propose a VN allocation model for multi-tenant data centers and formulate a problem that deals with the bandwidth loss in a single VN due a single SN failure. We conduct numerical simulations (with the setting that has 1.7×108bit/s bandwidth demand on each VN, (denoted by Ci)). When each node in each VN is scattered and mapped to an individual physical server, each VN can have the minimum bandwidth loss (5.3×102bit/s (3.0×10-6×Ci)) but the maximum required bandwidth between physical servers (1.0×109bit/s (5.7×Ci)). The balance between the bandwidth loss and the required physical resources can be optimized by assigning every four nodes of each VN to an individual physical server, meaning that we minimize the bandwidth loss without over-provisioning of core switches.

For an odd prime p and a positive integer r, new classes of binary sequences with period pr+1 are proposed from Euler quotients in this letter, which include several known classes of binary sequences derived from Fermat quotients and Euler quotients as special cases. The advantage of the new constructions is that they allow one to choose their support sets freely. Furthermore, with some constrains on the support set, the new sequences are proved to possess large linear complexities under the assumption of 2p-1 ≢ 1 mod p2.

OSEK/VDX, a standard for an automobile OS, has been widely adopted by many manufacturers to design and develop a vehicle-mounted OS. With the increasing functionalities in vehicles, more and more complex applications are be developed based on the OSEK/VDX OS. However, how to ensure the reliability of developed applications is becoming a challenge for developers. To ensure the reliability of developed applications, model checking as an exhaustive technique can be applied to discover subtle errors in the development process. Many model checkers have been successfully applied to verify sequential software and general multi-threaded software. However, it is hard to directly use existing model checkers to precisely verify OSEK/VDX applications, since the execution characteristics of OSEK/VDX applications are different from the sequential software and general multi-threaded software. In this paper, we describe and develop an approach to translate OSEK/VDX applications into sequential programs in order to employ existing model checkers to precisely verify OSEK/VDX applications. The value of our approach is that it can be considered as a front-end translator for enabling existing model checkers to verify OSEK/VDX applications.

This paper presents a method of imaging a two-dimensional section of a walking person using multiple Doppler radar systems. Although each simple radar system consists of only two receivers, different radial speeds allow target positions to be separated and located. The signal received using each antenna is processed employing time-frequency analysis, which separates targets in the time-range-velocity space. This process is followed by a direction-of-arrival estimation employing interferometry. The data obtained using the multiple radar systems are integrated using a clustering algorithm and a target-tracking algorithm. Through realistic simulations, we demonstrate the remarkable performance of the proposed imaging method in generating a clear outline image of a human target in unknown motion.

In a previous paper, we proposed a rescue support system for victims buried in an earthquake disaster by constructing an ad-hoc network using home-server based smart homes. However, this system has the following two problems: i) it cannot ensure sufficient density of home servers to realize adequate WLAN coverage, ii) the system does not consider areas in which home servers cannot be used such as parks and factories, for example. In this paper, we propose a new method using a delay tolerant network (DTN) technique. In this method, rescuers (such as rescue teams) with mobile devices relay information between disconnected networks by walking around during rescue activities. For a performance evaluation, we performed simulation experiments using a map of Abeno-ku, Osaka. From our results, we show that the proposed method increases the information acquisition rate, and that the network can be maintained. We also quantitatively show the penetration rate of smart homes needed for our system. In addition, we show that the rescue request system is more effective than other systems, and the method with the mobile device relay is better than without this method.

Network Coding-based Epidemic Routing (NCER) facilitates the reduction of data delivery delay in Delay Tolerant Networks (DTNs). The intrinsic reason lies in that the network coding paradigm avoids competitions for transmission opportunities between segmented packets of a large data file. In this paper, we focus on the impact of transmission competitions on the delay performance of NCER when multiple data files exist. We prove analytically that when competition occurs, transmitting the least propagated data file is optimal in the sense of minimizing the average data delivery delay. Based on such understanding, we propose a family of competition avoidance policies, namely the Least Propagated First (LPF) policies, which includes a centralized, a distributed, and a modified variants. Numerical results show that LPF policies can achieve at least 20% delay performance gain at different data traffic rates, compared with the policy currently available.

Optical single sideband (SSB) modulation with the Mach-Zehnder (MZ) interferometer was realized by integrating the modulation electrode with the branch-line coupler (BLC) as a 90-degree hybrid onto the modulator substrate. In this paper, BLCs of the microsrtip-line structure were miniaturized on modulator substrates, LiNbO3 (LN), to realize more compact optical SSB modulators. We introduced two techniques of miniaturizing the BLC, one is using periodically installed open-circuited stabs and the other is installing series capacitors. Compared with a conventional pattern of the BLC, an area of the miniaturized BLC by using periodically installed open-circuited stubs was reduced to about 50%, and that by installing series capacitors was done to about 60%. The operation of these miniaturized BLCs was experimentally confirmed as the 90-degree hybrid at around 10GHz. Output ports of each miniaturized BLC were directly connected with the modulation electrode on the modulator substrate. Thereby, we fabricated two types of compact SSB modulators for 1550nm light wavelength. In the experiments, the optical SSB modulation was successfully confirmed by the output light spectra and the sideband suppression ratio of more than 30dB were observed.

RXv2 is the new generation of Renesas's processor architecture for microcontrollers with high-capacity flash memory. An enhanced instruction set and pipeline structure with an advanced fetch unit (AFU) provide an effective balance between power consumption performance and high processing performance. Enhanced instructions such as DSP function and floating point operation and a five-stage dual-issue pipeline synergistically boost the performance of digital signal applications. The RXv2 processor delivers 1.9 - 3.7 the cycle performance of the RXv1 in these applications. The decrease of the number of Flash memory accesses by AFU is a dominant determiner of reducing power consumption. AFU of RXv2 benefits from adopting branch target cache, which has a comparatively smaller area than that of typical cache systems. High code density delivers low power consumption by reducing instruction memory bandwidth. The implementation of RXv2 delivers up to 46% reduction in static code size, up to 30% reduction in dynamic code size relative to RISC architectures. RXv2 reaches 4.0 Coremark per MHz and operates up to 240MHz. The RXv2 processor delivers approximately more than 2.2 - 5.7x the power efficiency of the RXv1. The RXv2 microprocessor achieves the best possible computing performance in various applications such as building automation, medical, motor control, e-metering, and home appliances which lead to the higher memory capacity, frequency and processing performance.

A miniaturized patch hybrid coupler with arbitrary power ratio and impedance transformation is proposed and designed by loading a pair of asymmetric cross slots on a squared patch resonator. To obtain the arbitrary power ratio and impedance transformation, the rectangular size of stepped slot ends should be well designed to be asymmetry and thus to obtain the different inductive loadings along two current paths. Theoretically, the equivalent transmission line model is first developed to understand the physical relationship between the patch and traditional branch-line hybrids. The matching/isolation and power ratio conditions are then derived at center frequency. By following a detailed design guideline, a prototype of the hybrid with 1:2 power ratio and 1:1.3 impedance transformation is designed and fabricated at 4.2 GHz. The measured results show a good agreement with simulated results, where the measured -10 dB impedance bandwidth achieves 18% and the bandwidth of 90°±6° phase difference is about 35% in a frequency range from 3.5 GHz to 5 GHz.

We propose a novel bias-free adaptive beamformer employing an affine projection algorithm with the optimal regularization parameter. The generalized sidelobe canceller affine projection algorithm suffers from a bias of a weight vectors under the condition of no reference signals for output of an array in the beamforming application. First, we analyze the bias in the algorithm and prove that the bias can be eliminated through a large regularization parameter. However, this causes slow convergence at the initial state, so the regularization parameter should be controlled. Through the optimization of the regularization parameter, the proposed method achieves fast convergence without the bias at the steady-state. Experimental results show that the proposed beamformer not only removes the bias but also achieves both fast convergence and high steady-state output signal-to-interference-plus-noise ratio.

This report describes a robust method of instantaneous heart rate (IHR) extraction from noisy electrocardiogram (ECG) signals. Generally, R-waves are extracted from ECG using a threshold to calculate the IHR from the interval of R-waves. However, noise increases the incidence of misdetection and false detection in wearable healthcare systems because the power consumption and electrode distance are limited to reduce the size and weight. To prevent incorrect detection, we propose a short-time autocorrelation (STAC) technique. The proposed method extracts the IHR by determining the search window shift length which maximizes the correlation coefficient between the template window and the search window. It uses the similarity of the QRS complex waveform beat-by-beat. Therefore, it has no threshold calculation process. Furthermore, it is robust against noisy environments. The proposed method was evaluated using MIT-BIH arrhythmia and noise stress test databases. Simulation results show that the proposed method achieves a state-of-the-art success rate of IHR extraction in a noise stress test using a muscle artifact and a motion artifact.

This paper presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.

We report the energy-efficient optical input interface using NbN superconducting nanowire-based optical-to-electrical (SN-OE) converters for a single-flux-quantum (SFQ) data processing system. The SN-OE converters with small active areas ranging from 1$, imes,$1 to 10$, imes,$10,$mu$m$^2$ were fabricated to improve the recovery time by reducing the kinetic inductance of the nanowire. The SN-OE with the smallest area of 1$, imes,$1 $mu$m$^2$ showed the recovery time of around 0.3 ns, while its detection efficiency for a single photon was reduced below 0.1% due to insufficient coupling efficiency with a single-mode optical fiber. However, the optical power dependence of the error rate of this device showed that the required optical power to achieve the error rate below $10^{-12}$ at 10 GHz operation is as large as 70 $mu$W, which is still one order of magnitude lower than semiconductor photo diodes. We also demonstrated the operation of the SN-OE converters combined with the SFQ readout circuit and confirmed the operating speed up to 77~MHz.

Due to increasing demand for machine-to-machine (M2M) communication, simultaneous connections for many terminals are requested for current wireless communication systems. Interleave division multiple access (IDMA) has superior multiuser detection performance and attains high data transmission efficiency in multiuser communications. This paper describes the VLSI implementation of an interference canceller for OFDM-IDMA systems. The conventional architecture decreases a throughput in pipeline processing due to wait time occurring in interleave and deinterleave memory units. The proposed architecture adopts dual-frame processing to solve the problem of the wait time and achieves a high utilization ratio in pipeline stage operation. In the implementation results, the proposed architecture has reduced circuit area and power consumption by 25% and 41% for BPSK demodulation and 33% and 44% for QPSK demodulation compared with the conventional architecture on the same throughput condition.

This paper describes an architectural design and related services of a new Japanese academic backbone network, called SINET5, which will be launched in April 2016. The network will cover all 47 prefectures with 100-Gigabit Ethernet technology and connect each pair of prefectures with a minimized latency. This will enable users to leverage evolving cloud-computing powers as well as draw on a high-performance platform for data-intensive applications. The transmission layer will form a fully meshed, SDN-friendly, and reliable network. The services will evolve to be more dynamic and cloud-oriented in response to user demands. Cyber-security measures for the backbone network and tools for performance acceleration and visualization are also discussed.

The combination of a halogen-free solvent 1,2,4-trimethylbenzene and unmodified fullerene potentially provides a way to develop environmentally-friendly and cost-effective solution-processed organic photocells. In this paper, the thermal annealing effect on the optical absorption spectra in poly(3-hexylthiophene):unmodified-C$_{60}$ composites with various compositions is reported. It is found that the onset temperature of the absorption spectrum change is higher in the composites with higher fullerene content. It is speculated that strong interaction between the polymer main chain and C$_{60}$ tends to suppress the reorientation of polymer main chains in a composite with high C$_{60}$ content.

In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their design framework for intellectual property (IP) cores in system-on-chip (SoC). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault avoidance, and a configuration mechanism for single-cycle reconfiguration. In addition, we utilize routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGAs and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 1.82 times the area and 1.11 times the delay compared with traditional island-style FPGAs. At the same time, our FPGA shows a higher fault tolerant performance.

Financial exchanges provide market data feeds to update their members about changes in the market. Feed messages are often used in time-critical automated trading applications, and two identical feeds (A and B feeds) are provided in order to reduce message loss. A key challenge is to support A/B line arbitration efficiently to compensate for missing packets, while offering flexibility for various operational modes such as prioritising for low latency or for high data reliability. This paper presents a reconfigurable acceleration approach for A/B arbitration operating at the network level, capable of supporting any messaging protocol. Two modes of operation are provided simultaneously: one prioritising low latency, and one prioritising high reliability with three dynamically configurable windowing methods. We also present a model for message feed processing latencies that is useful for evaluating scalability in future applications. We outline a new low latency, high throughput architecture and demonstrate a cycle-accurate testing framework to measure the actual latency of packets within the FPGA. We implement and compare the performance of the NASDAQ TotalView-ITCH, OPRA and ARCA market data feed protocols using a Xilinx Virtex-6 FPGA. For high reliability messages we achieve latencies of 42ns for TotalView-ITCH and 36.75ns for OPRA and ARCA. 6ns and 5.25ns are obtained for low latency messages. The most resource intensive protocol, TotalView-ITCH, is also implemented in a Xilinx Virtex-5 FPGA within a network interface card; it is used to validate our approach with real market data. We offer latencies 10 times lower than an FPGA-based commercial design and 4.1 times lower than the hardware-accelerated IBM PowerEN processor, with throughputs more than double the required 10Gbps line rate.