Web-based social engineering (SE) attacks manipulate users to perform specific actions, such as downloading malware and exposing personal information. Aiming to effectively lure users, some SE attacks, which we call multi-step SE attacks, constitute a sequence of web pages starting from a landing page and require browser interactions at each web page. Also, different browser interactions executed on a web page often branch to multiple sequences to redirect users to different SE attacks. Although common systems analyze only landing pages or conduct browser interactions limited to a specific attack, little effort has been made to follow such sequences of web pages to collect multi-step SE attacks. We propose STRAYSHEEP, a system to automatically crawl a sequence of web pages and detect diverse multi-step SE attacks. We evaluate the effectiveness of STRAYSHEEP's three modules (landing-page-collection, web-crawling, and SE-detection) in terms of the rate of collected landing pages leading to SE attacks, efficiency of web crawling to reach more SE attacks, and accuracy in detecting the attacks. Our experimental results indicate that STRAYSHEEP can lead to 20% more SE attacks than Alexa top sites and search results of trend words, crawl five times more efficiently than a simple crawling module, and detect SE attacks with 95.5% accuracy. We demonstrate that STRAYSHEEP can collect various SE attacks, not limited to a specific attack. We also clarify attackers' techniques for tricking users and browser interactions, redirecting users to attacks.

In this paper, we improve upon the automatic building extraction method, which uses a variational inference Gaussian mixture model for performing color clustering, by accelerating its computational speed. The improved method decreases the computational time using an image with reduced resolution upon applying color clustering. According to our experiment, in which we used 106 scenery images, the improved method could extract buildings at a rate 86.54% faster than that of the conventional methods. Furthermore, the improved method significantly increased the extraction accuracy by 1.8% or more by preventing over-clustering using the reduced image, which also had a reduced number of the colors.

High level synthesis (HLS) is a source-code-driven Register Transfer Level (RTL) design tool, and the performance, the power consumption, and the area of a generated RTL are limited partly by the description of a HLS input source code. In order to break through such kind of limitation and to get a further optimized RTL, the optimization of the input source code is indispensable. Routing congestion is one of such problems we need to consider the refinement of a HLS input source code. In this paper, we propose a novel HLS flow that performs code improvements by detecting congested parts directly from HLS input source code without using physical logic synthesis, and regenerating the input source code for HLS. In our approach, the origin of the wire congestion is detected from the HLS input source code by applying pattern matching on Program-Dependence Graph (PDG) constructed from the HLS input source code, the possibility of wire congestion is reported.

We propose a new design approach to improve the computational efficiency of an optimal design of optical waveguide devices utilizing coupled mode theory (CMT) and a neural network (NN). Recently, the NN has begun to be used for efficient optimal design of optical devices. In this paper, the eigenmode analysis required in the CMT is skipped by using the NN, and optimization with an evolutionary algorithm can be efficiently carried out. To verify usefulness of our approach, optimal design examples of a wavelength insensitive 3dB coupler, a 1 : 2 power splitter, and a wavelength demultiplexer are shown and their transmission properties obtained by the CMT with the NN (NN-CMT) are verified by comparing with those calculated by a finite element beam propagation method (FE-BPM).

In the typical unmanned aircraft system (UAS), several unmanned aerial vehicles (UAVs) traveling at a velocity of 40-100km/h and with altitudes of 150-1,000m will be used to cover a wide service area. Therefore, Doppler shifts occur in the carrier frequencies of the transmitted and received signals due to changes in the line-of-sight velocity between the UAVs and the terrestrial terminal. By observing multiple Doppler shift values for different UAVs or observing a single UAV at different local times, it is possible to detect the user position on the ground. We conducted computer simulations for evaluating user position detection accuracy and Doppler shift distribution in several flight models. Further, a positioning accuracy index (PAI), which can be used as an index for position detection accuracy, was proposed as the absolute value of cosine of the inner product between two gradient vectors formed by Doppler shifts to evaluate the relationship between the location of UAVs and the position of the user. In this study, a maximum positioning error estimation method related to the PAI is proposed to approximate the position detection accuracy. Further, computer simulations assuming a single UAV flying on the curved routes such as sinusoidal routes with different cycles are conducted to clarify the effectiveness of the flight route in the aspects of positioning accuracy and latency by comparing with the conventional straight line fight model using the PAI and the proposed maximum positioning error estimation method.

Many studies of deep neural networks have reported inference accelerators for improved energy efficiency. We propose methods for further improving energy efficiency while maintaining recognition accuracy, which were developed by the co-design of a filter-by-filter quantization scheme with variable bit precision and a hardware architecture that fully supports it. Filter-wise quantization reduces the average bit precision of weights, so execution times and energy consumption for inference are reduced in proportion to the total number of computations multiplied by the average bit precision of weights. The hardware utilization is also improved by a bit-parallel architecture suitable for granularly quantized bit precision of weights. We implement the proposed architecture on an FPGA and demonstrate that the execution cycles are reduced to 1/5.3 for ResNet-50 on ImageNet in comparison with a conventional method, while maintaining recognition accuracy.

This paper investigates the performance of interleave division multiple access (IDMA)-based random access with various interference canceller structures in order to support massive machine-type communications (mMTC) in the fifth generation (5G) mobile communication system. To support massive connectivity in the uplink, a grant-free and contention-based multiple access scheme is essential to reduce the control signaling overhead and transmission latency. To suppress the packet loss due to collision and to achieve multi-packet reception, non-orthogonal multiple access (NOMA) with interference cancellation at the base station receiver is essential. We use IDMA and compare various interference canceller structures such as the parallel interference canceller (PIC), successive interference canceller (SIC), and their hybrid from the viewpoints of the error rate and decoding delay time. Based on extensive computer simulations, we show that IDMA-based random access is a promising scheme for supporting mMTC and the PIC-SIC hybrid achieves a good tradeoff between the error rate and decoding delay time.

Fresh Tea Shoot Maturity Estimation (FTSME) is the basement of automatic tea picking technique, determines whether the shoot can be picked. Unfortunately, the ambiguous information among single labels and uncontrollable imaging condition lead to a low FTSME accuracy. A novel Fresh Tea Shoot Maturity Estimating method via multispectral imaging and Deep Label Distribution Learning (FTSME-DLDL) is proposed to overcome these issues. The input is 25-band images, and the output is the corresponding tea shoot maturity label distribution. We utilize the multiple VGG-16 and auto-encoding network to obtain the multispectral features, and learn the label distribution by minimizing the Kullback-Leibler divergence using deep convolutional neural networks. The experimental results show that the proposed method has a better performance on FTSME than the state-of-the-art methods.

Some non-acoustic modalities have the ability to reveal certain speech attributes that can be used for synthesizing speech signals without acoustic signals. This study validated the use of ultrasonic Doppler frequency shifts caused by facial movements to implement a silent speech interface system. A 40kHz ultrasonic beam is incident to a speaker's mouth region. The features derived from the demodulated received signals were used to estimate the speech parameters. A nonlinear regression approach was employed in this estimation where the relationship between ultrasonic features and corresponding speech is represented by deep neural networks (DNN). In this study, we investigated the discrepancies between the ultrasonic signals of audible and silent speech to validate the possibility for totally silent communication. Since reference speech signals are not available in silently mouthed ultrasonic signals, a nearest-neighbor search and alignment method was proposed, wherein alignment was achieved by determining the optimal pair of ultrasonic and audible features in the sense of a minimum mean square error criterion. The experimental results showed that the performance of the ultrasonic Doppler-based method was superior to that of EMG-based speech estimation, and was comparable to an image-based method.

This paper presents the feasibility of a capacitive coupler utilizing an electric double layer for wireless power transfer under seawater. Since seawater is an electrolyte solution, an electric double layer (EDL) is formed on the electrode surface of the coupler in direct current. If the EDL can be utilized in radio frequency, it is possible that high power transfer efficiency can be achieved under seawater because a high Q-factor can be obtained. To clarify this, the following steps need taking; First, measure the frequency characteristics of the complex permittivity in seawater and elucidate the behaviors of the EDL from the results. Second, clarify that EDL leads to an improvement in the Q-factor of seawater. It will be shown in this paper that capacitive coupling by EDL occurs using two kinds of the coupler models. Third, design a coupler with high efficiency as measured by the Q-factor and relative permittivity of EDL. Last, demonstrate that the designed coupler under seawater can achieve over 85% efficiency at a transfer distance of 5 mm and feasibility of the coupler with EDL.

The triaxial accelerometer is one of the most important sensors for human activity recognition (HAR). It has been observed that the relations between the axes of a triaxial accelerometer plays a significant role in improving the accuracy of activity recognition. However, the existing research rarely focuses on these relations, but rather on the fusion of multiple sensors. In this paper, we propose a data fusion-based convolutional neural network (CNN) approach to effectively use the relations between the axes. We design a single-channel data fusion method and multichannel data fusion method in consideration of the diversified formats of sensor data. After obtaining the fused data, a CNN is used to extract the features and perform classification. The experiments show that the proposed approach has an advantage over the CNN in accuracy. Moreover, the single-channel model achieves an accuracy of 98.83% with the WISDM dataset, which is higher than that of state-of-the-art methods.

The advancement of multicore technology has made hundreds or even thousands of cores processor on a single chip possible. However, on a larger scale multicore, a hardware-based cache coherency mechanism becomes overwhelmingly complicated, hot, and expensive. Therefore, we propose a software coherence scheme managed by a parallelizing compiler for shared-memory multicore systems without a hardware cache coherence mechanism. Our proposed method is simple and efficient. It is built into OSCAR automatic parallelizing compiler. The OSCAR compiler parallelizes the coarse grain task, analyzes stale data and line sharing in the program, then solves those problems by simple program restructuring and data synchronization. Using our proposed method, we compiled 10 benchmark programs from SPEC2000, SPEC2006, NAS Parallel Benchmark (NPB), and MediaBench II. The compiled binaries then are run on Renesas RP2, an 8 cores SH-4A processor, and a custom 8-core Altera Nios II system on Altera Arria 10 FPGA. The cache coherence hardware on the RP2 processor is only available for up to 4 cores. The RP2's cache coherence hardware can also be turned off for non-coherence cache mode. The Nios II multicore system does not have any hardware cache coherence mechanism; therefore, running a parallel program is difficult without any compiler support. The proposed method performed as good as or better than the hardware cache coherence scheme while still provided the correct result as the hardware coherence mechanism. This method allows a massive array of shared memory CPU cores in an HPC setting or a simple non-coherent multicore embedded CPU to be easily programmed. For example, on the RP2 processor, the proposed software-controlled non-coherent-cache (NCC) method gave us 2.6 times speedup for SPEC 2000 “equake” with 4 cores against sequential execution while got only 2.5 times speedup for 4 cores MESI hardware coherent control. Also, the software coherence control gave us 4.4 times speedup for 8 cores with no hardware coherence mechanism available.

To estimate angle, velocity, and range information of multiple targets jointly in FMCW MIMO radar, two-dimensional (2D) MUSIC with matched filtering and FFT algorithm is proposed. By reformulating the received FMCW signal of the colocated MIMO radar, we exploit 2D MUSIC to estimate the angle and Doppler frequency of multiple targets. Then by using a matched filter together with the estimated angle and Doppler frequency and FFT operation, the range of the target is estimated. To effectively estimate the parameters of multiple targets with large distance differences, we also propose a successive interference cancellation method that uses the orthogonal projection. That is, rather than estimating the multiple target parameters simultaneously using 2D MUSIC, we estimate the target parameters sequentially, in which the parameters of the target having strongest reflected power are estimated first and then, their effect on the received signal is canceled out by using the orthogonal projection. Simulations verify the performance of the proposed algorithm.

Utilization of local memory from real-time embedded systems to high performance systems with multi-core processors has become an important factor for satisfying hard deadline constraints. However, challenges lie in the area of efficiently managing the memory hierarchy, such as decomposing large data into small blocks to fit onto local memory and transferring blocks for reuse and replacement. To address this issue, this paper presents a compiler optimization method that automatically manage local memory of multi-core processors. The method selects and maps multi-dimensional data onto software specified memory blocks called Adjustable Blocks. These blocks are hierarchically divisible with varying sizes defined by the features of the input application. Moreover, the method introduces mapping structures called Template Arrays to maintain the indices of the decomposed multi-dimensional data. The proposed work is implemented on the OSCAR automatic parallelizing compiler and evaluations were performed on the Renesas RP2 8-core processor. Experimental results from NAS Parallel Benchmark, SPEC benchmark, and multimedia applications show the effectiveness of the method, obtaining maximum speed-ups of 20.44 with 8 cores utilizing local memory from single core sequential versions that use off-chip memory.

In this paper, we extend the notion of bijective connection graphs to introduce directed bijective connection graphs. We propose algorithms that solve the node-to-set node-disjoint paths problem and the node-to-node node-disjoint paths problem in a directed bijective connection graph. The time complexities of the algorithms are both O(n4), and the maximum path lengths are both 2n-1.

The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.

In wireless networks, efficient topology improves the performance of network protocols. The previous research mainly focuses on how to construct a cost-efficient network structure from a static and connected topology. Due to lack of continuous connectivity in the underlying topology, most traditional topology control methods are not applicable to the delay or disruption tolerant networks (DTNs). In this paper, we consider the topology control problem in a predictable DTN where the dynamic topology is known a priori or can be predicted over time. First, this dynamic topology is modeled by a directed space-time graph that includes spatial and temporal information. Second, the topology control problem of the predictable DTN is formulated as building a sparse structure. For any pair devices, there is an efficient path connecting them to improve the efficiency of the generated structure. Then, a topology control strategy is proposed for this optimization problem by using a kth shortest paths algorithm. Finally, simulations are conducted on random networks and a real-world DTN tracing date. The results demonstrate that the proposed method can significantly improve the efficiency of the generated structure and reduce the total cost.

Real-time 3D players tracking plays an important role in sports analysis, especially for the live services of sports broadcasting, which have a strict limitation on processing time. For these kinds of applications, 3D trajectories of players contribute to high-level game analysis such as tactic analysis and commercial applications such as TV contents. Thus real-time implementation for 3D players tracking is expected. In order to achieve real-time for 60fps videos with high accuracy, (that means the processing time should be less than 16.67ms per frame), the factors that limit the processing time of target algorithm include: 1) Large image area of each player. 2) Repeated processing of multiple players in multiple views. 3) Complex calculation of observation algorithm. To deal with the above challenges, this paper proposes a representative spatial selection and temporal combination based real-time implementation for multi-view volleyball players tracking on the GPU device. First, the representative spatial pixel selection, which detects the pixels that mostly represent one image region to scale down the image spatially, reduces the number of processing pixels. Second, the representative temporal likelihood combination shares observation calculation by using the temporal correlation between images so that the times of complex calculation is reduced. The experiments are based on videos of the Final and Semi-Final Game of 2014 Japan Inter High School Games of Men's Volleyball in Tokyo Metropolitan Gymnasium. On the GPU device GeForce GTX 1080Ti, the tracking system achieves real-time on 60fps videos and keeps the tracking accuracy higher than 97%.

Conventional sequential processing on software with a general purpose CPU has become significantly insufficient for certain heavy computations due to the high demand of processing power to deliver adequate throughput and performance. Due to many reasons a high degree of interest could be noted for high performance real time video processing on embedded systems. However, embedded processing platforms with limited performance could least cater the processing demand of several such intensive computations in computer vision domain. Therefore, hardware acceleration could be noted as an ideal solution where process intensive computations could be accelerated using application specific hardware integrated with a general purpose CPU. In this research we have focused on building a parallelized high performance application specific architecture for such a hardware accelerator for HOG-SVM computation implemented on Zynq 7000 FPGA. Histogram of Oriented Gradients (HOG) technique combined with a Support Vector Machine (SVM) based classifier is versatile and extremely popular in computer vision domain in contrast to high demand for processing power. Due to the popularity and versatility, various previous research have attempted on obtaining adequate throughput on HOG-SVM. This research with a high throughput of 240FPS on single scale on VGA frames of size 640x480 out performs the best case performance on a single scale of previous research by approximately a factor of 3-4. Further it's an approximately 15x speed up over the GPU accelerated software version with the same accuracy. This research has explored the possibility of using a novel architecture based on deep pipelining, parallel processing and BRAM structures for achieving high performance on the HOG-SVM computation. Further the above developed (video processing unit) VPU which acts as a hardware accelerator will be integrated as a co-processing peripheral to a host CPU using a novel custom accelerator structure with on chip buses in a System-On-Chip (SoC) fashion. This could be used to offload the heavy video stream processing redundant computations to the VPU whereas the processing power of the CPU could be preserved for running light weight applications. This research mainly focuses on the architectural techniques used to achieve higher performance on the hardware accelerator and on the novel accelerator structure used to integrate the accelerator with the host CPU.

A non-photorealistic rendering method has been proposed for generating oil-film-like images from photographic images by bilateral infra-envelope filter. The conventional method has a disadvantage that it takes much time to process. We propose a method for generating oil-film-like images that can be processed faster than the conventional method. The proposed method uses an iterative process with upper and lower smoothing filters. To verify the effectiveness of the proposed method, we conduct experiments using Lenna image. As a result of the experiments, we show that the proposed method can process faster than the conventional method.